Two things are striking if one right-arrows through each year from the beginning: the wall for local circuit latency hit around 2005/2006, and the limitations the speed of light puts on global latency from the beginning. The harsh takeaway I get from these presentations is that the speed of light is just not as stellar as we'd like, and that's a challenge.
Anyone knows why the L caches could not simply be as large as our current main memory, let's say 16gb L2 cache and 4gb L1 chache directly on the die - would that be possible if price would not matter? What kind of problem is this?
Basically, SRAM costs more to make. The memory fabs also use less expensive tech with just a few layers vs the 10 or whatever absurd number CPU's and their fabs require. There's a company that built a CPU for memory fabs specifically to leverage what they said was a 100x cost difference.
There's been some use, like in IBM's high-end POWER, of slower memories for L3 or whatever that are WAY larger but still on chip. I'm not sure how that panned out in terms of results.
yes, L cache for sure is more delicate than a ram that you clip to the motherboard with 1000x the size - so it's only a cost factor? what is the other reason to not simply increase the cpu die size and put lots of cache next to it?
the ibm high power you mentioned doesnt seem to have large cache sizes, it's just double or triple the usual amount, 8mb L3 chache is not even close to a gigabyte, it's like ram in 1995, and that is a power cpu architecture? My 6 year old cheap amd cpu has 2mb L3.
It's a price-, feature-, and energy-sensitive market. You can't just max one metric without caring about effects. Such things can cost companies. Far as cache sizes, I was referring to this:
POWER7+ used embedded DRAM to vastly up the cache size vs other processors. The POWER8 apparently mixes internal and external caches or something. I'm not sure. In any case, it's not the few MB to 8MB that's more common: it starts over 10x higher than that using a much slower tech. Also note that it's a 15 layer chip with each layer costing extra silicon and masks vs 3 or so for memory fabs.
Note: A mask set might be a few million dollars with silicon wafers at around $3,000 a piece. So, a 5x reduction in masks/silicon might make a substantial difference in price of prototyping and production. ;)
You can also run out of space on the die. Silicon die sizes are limited by physics and economic considerations.
You can't put too many power hungry transistors next to each other and still be able to cool the die.
If problems are random over the area, then if you increase the die size, there are more errors per die, which drops your yield.
Why not make the DRAM out of SRAM? I think the answer is that the latency to access the DIMMs won't go down (it's dominated by the distance from the processor to the modules).
Ulrich Drepper has a good paper on the topic:
https://www.akkadia.org/drepper/cpumemory.pdf
It's a few years old, so the discussions of North/Southbridges is obsolete, but the discussion of RAM tech (p. 5) is fundamental, and hasn't changed too much (to my knowledge).
I overlooked size/errors. Good points. I now remember reading about such issues under banner of Design for Manufacturing where they had those considerations in the design flow. Far as paper, I'll look at it later. :)
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Basically, SRAM costs more to make. The memory fabs also use less expensive tech with just a few layers vs the 10 or whatever absurd number CPU's and their fabs require. There's a company that built a CPU for memory fabs specifically to leverage what they said was a 100x cost difference.
There's been some use, like in IBM's high-end POWER, of slower memories for L3 or whatever that are WAY larger but still on chip. I'm not sure how that panned out in terms of results.
the ibm high power you mentioned doesnt seem to have large cache sizes, it's just double or triple the usual amount, 8mb L3 chache is not even close to a gigabyte, it's like ram in 1995, and that is a power cpu architecture? My 6 year old cheap amd cpu has 2mb L3.
here is a ibm power spec sheet: http://www-01.ibm.com/common/ssi/cgi-bin/ssialias?subtype=SP...
http://www.theregister.co.uk/2012/10/03/ibm_power7_plus_serv...
https://en.wikipedia.org/wiki/POWER8
POWER7+ used embedded DRAM to vastly up the cache size vs other processors. The POWER8 apparently mixes internal and external caches or something. I'm not sure. In any case, it's not the few MB to 8MB that's more common: it starts over 10x higher than that using a much slower tech. Also note that it's a 15 layer chip with each layer costing extra silicon and masks vs 3 or so for memory fabs.
Note: A mask set might be a few million dollars with silicon wafers at around $3,000 a piece. So, a 5x reduction in masks/silicon might make a substantial difference in price of prototyping and production. ;)