It's a neat idea but I doubt it will happen. He has to build and test all the components, from MCU to I/O, plus fab it all for $20,000. By himself. I might believe it for a FPGA project but not an ASIC.
So, it's a good project. I've promoted doing a RISC-V dropin for Arduino's. I see the vision. He might just be better off tweaking some stuff on OpenCores, esp changing decoder for RISC-V, then integrating it. Get money some other way to cover testing the pieces in shuttle runs. Once they all work, then test the whole thing with a big run that produces a big batch of chips.
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[ 2.7 ms ] story [ 17.3 ms ] threadGoogling his name turns up a blog here - http://blog.the-leviathan.ch/ - which has two mentions of RISC-V but not much else about relevant projects.
Has anyone else found any supporting documentation?
So, it's a good project. I've promoted doing a RISC-V dropin for Arduino's. I see the vision. He might just be better off tweaking some stuff on OpenCores, esp changing decoder for RISC-V, then integrating it. Get money some other way to cover testing the pieces in shuttle runs. Once they all work, then test the whole thing with a big run that produces a big batch of chips.
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