This is 5 years from now that transistors won't shrink anymore. Computers stopped a while ago having higher clock speeds. More integration, wider data paths compensated to some degree. The discussed alternatives like vertical sound in my ears fairly exotic for an industry that has been shrinking, shrinking and shrinking the nodes as the main mode of technical progress.
The potential impact is game-changing. I really wonder how this is going to shape where investments in IT go.
The problem is that the gap between what the hardware guys are able to offer and what software can explorer is getting bigger and bigger.
Hence why the explosion in IoT nowadays, that is nothing new. Everyone with some EE background has been playing with microcontrolers since the early 2000.
However we have reached a point where to make such tiny computers, more powerful than any of my PCs at the university, is ridiculously cheap.
A computer like the Arduino used to cost more than 100 euros back in the day, now I can buy one for 5 euros and who cares if it burns.
On the other side of the spectrum we have CPUs like the Nvidia Titan X, which 99% of the computing population can barely make it get out of idle state.
So unless one is an heavy gamer, doing Fintech, VR or AI research there is hardly anything new processors can offer over the existing computing workloads.
So I guess it isn't stop shrinking as such, but also if it will still be economically viable to continue that route until a new computing paradigm emerges (e.g. Quantum or whatever)
I really wonder how this is going to shape where investments in IT go.
Hopefully we'll start to see even more emphasis on optimisation, possibly revived interest in Asm while compilers catch up... and then realise just how efficient software can really be.
I really hope for that. Working with Unix tools a lot, I appreciate these programs, that were already useful over thirty years ago.
The developer mindset needs to change as well. I seldom here people wondering about the sheer computing power of the systems they use.
Many developers also seem to get a kick out of building complex systems (with (most of the time too) many abstraction layers burning cpu cycles) - because they seem to believe building complex things somehow means having control over complexity - but I'm not sure about that.
Your wish will soon be granted: SIMD is a stage 3 proposal for JavaScript, already implemented in nightly versions of FF and Edge, coming to Chrome as well.
Does anybody know why the 2015 prevision go faster to 10nm than the 2013 one ? They take some delay at 14/16 nm but they want to keep the 10nm target for 2021 ?
Note that they bury an important concept deeper in the article:
The new report embraces these trends, predicting an end to traditional scaling—the shrinking of chip features—by the early 2020’s. But the idea that we’re now facing an end to Moore’s Law “is completely wrong,” Gargini says. ... If a company really wanted to, Gargini says, it could continue to make transistors smaller well into the 2020s, “but it’s more economic to go 3-D. That’s the message we wanted to send.”
Moore's law has always been down to economics - it was worth the industry's investment to develop more transistors per chip area for the next year. If that stops then it stops. Computers will keep getting faster and more powerful though by whatever means makes economic sense.
Right - but the subtle, and easy to miss message here, isn't that its not longer possible, or even economical to continue to increase density of transistors absent other opportunities, but that with the advent of 3D technologies, increasing the number of transistors per chip can be done more efficiently using 3D approaches. It may be, that once that approach has run it's course, the industry switches back to increasing density again.
Ultimately you hit a 2D density wall. I'd imagine it's harder to get more dense than one bit per several atoms. A silicon atom itself is 0.2nm, so ... not that far off of where we already are. That pretty much maxes out the thin-film 2D approach, and to pack in more, we'll need to go vertical. And to do that, we'll need to create novel fabrication technologies (unless they come up with some photo-lithography magic that I can't imagine right now), and, problematically, they'll need to deal with heat.
This is not to say that I am disagreeing with you on the switch-back-to-2d front, but I don't think we have much further to go on the 2d-density front.
Completely concur with you. The ITRS reports indicate that if 3D integration hadn't become the new mechanism for increasing transistor density, that gate-length reduction cycle would have run out of gas around 2028 - so about 12 years out regardless.
It remains to be seen we still have that 12 years of efficiency available to us after building 3D chips. I can easily imagine that heat distribution would be a real problem.
> I can easily imagine that heat distribution would be a real problem.
Given how much of a problem it already is in 2D where the entire die area simply radiates "up and out", I think that head might be the real problem. I don't know how one would build a 3D embedded heat-sink, you know, something like this with the transistors and and connective mesh all around [1]. Maybe it looks like a Menger sponge [2], but that looks tough too! :-)
First we need to cool the chips. We can increase cooling rate, using micro channels that carry water. Darpa verified that we can increase it to "1 kW/cm2 die-level heat flux with multiple local 30 kW/cm2 hot spots. This is about four to five times more heat per unit area than most current chips dissipate"[1]. Maybe we can do even better.
The thing is - it's expensive.
But than we can use this to build logic with memory on top ,and get huge bandwidth - and in multicore systems you could 100x performance in some algorithms , with easier programming. But this will be expensive.
But than we could start using those systems, building an ecosystem around them, generate money - and slowly, generation by generation with a moore's law like race, work on building photonics to greatly decrease power consumption - and hence cost.
That's at least the plan in [2].
Also relevant: ST microelectronics is in the final stages of opening a leading edge, commercial photonics fab.
Now we just need to find a way to build those microchannels stacked at every other layer or so without building fluid junction popping back-pressure! :-)
Or maybe just plan on doubling down on photonics (your #2 suggestion); that certainly makes switching energy (and heat) go way waaay down.
Isn't diamond a thermal 'short'? Rather than using liquid, why not use vapour deposition diamond to draw the heat down to a cold finger or TEC (Perltier cooler)?
I know if it was that easy we would already be doing it, but I'm hoping somebody knows why. Probably because interfacing the grown diamond to silicon creates interface stress that leads to cracking or...some other reason... :: mutters ::
Yup. Depending on, well, a number of factors related to doping and oxides and the like, usually even more. I'm just shooting for the right number of zeros in an overly optimistic boundary/wall hypothetical! :-)
Actually it will soon be physically impossible to continue 2D scaling. Even if you could operate a single-atom gate once you hit that limit you're done. We aren't that far away.
Not more efficiently. 3D here means running the IC through more fab steps to stack layers. This raises costs, which are roughly linear with the number of fab steps. It also hurts yield, although memory devices can be designed to tolerate errors.
3D stacking is mostly useful for parts that don't generate much heat. The inner layers have cooling problems. Flash memory, yes; CPUs, no.
Moore's Law was about increasing area density of transistors on a chip. Transistors got smaller and faster. Fabs got more expensive at each shrink, though. For a long time, the cost advantages of the shrink were a win over the increased fab cost. But that's ended. Fab cost ended up dominating the industry. There are only four high-end fab companies left.
The question for years is which limit would dominate - fab cost, heat dissipation, or, ultimately, the size of atoms and electrons. The first two are being reached now. Flash devices are already down to 10-20 significant electrons per storage cell, so there's not much room left there.
Atoms, electrons, and photons are just too big. There's no longer plenty of room at the bottom, as Feynman put it.
More efficiently in the sense that, on a ROI basis, there's now more R on the I of 3D stacking, than there is in the I of increasing transistor density.
Agreed that Moore's law was about increasing density of transistors on a chip - but you can do that in various ways. The article was clear to state, "Moore’s Law, he emphasizes, is simply a prediction about how many transistors can fit in a given area of IC—whether it’s done, as it has been for decades, in a single layer or by stacking multiple layers."
As a computer engineering student, I don't understand how adding more transistors to a cpu makes it faster, gpu's, sure. If I wire an 8-bit adder circuit, adding more transistors will definitely not make it process those bits faster.
There are many ways to create adders [0]. And other circuits for that matter. If you are willing to expend more transistors, you can decrease the propagation delay [1], that is, the delay until all outputs have settled to a stable value. Basically the propagation delay is the "longest path" from any input to any output and is a constraint on how fast the clock can go without messing up the calculations. Other ways to make a CPU faster, which costs transistors, is improved branch prediction and parallelism (modern CPUs execute a lot in parallel, even single cores. If there is a conditional branch and it guessed wrong, it has to flush all the wrong stuff it calculated. But there are still speed gains if the branch prediction is okay.)
Sure. The core of any particular implementation of an arithmetic operation isn't going to get faster with more transistors, but: 1) There is "stuff" before and after the arithmetic operation that matter such as pipelines, cache pre-fetch and instruction branch prediction; 2) There is more than one way to implement an arithmetic function (such as an adder) if you have more/cheap/free transistors, such as the carry look-ahead adder[1].
You can build a second 8-bit adder, plus a bunch of logic to identify add instructions which don't depend on each other, then execute two adds simultaneously.
Modern CPUs can execute several instructions per clock cycle doing things like this.
If you are allowed to use many transistors, you could create a carry look-ahead adder which would be faster. ;)
There are more ways to speed up your CPU, like identifying instructions that can be executed independently and issue them in parallel, use caches to speed up loading, etc.
1) Smaller circuits (used to?) have less capacitance and smaller voltages. Smaller voltages and capacitance enables higher clock-rate with same power consumption (chips don't melt)
2) Spending more transistors for pipelines and multiple execution units in the same core speeds up the processing. Single instruction takes at least five clock cycles from start to finish. With pipelines it's possible to finish one instruction per cycle. With multiple execution units it's possible to finish more than one instruction per cycle. This all from a single core.
3) Cache. Lots of it, different levels. Accessing external memory is very slow. Main cache reference takes about 1 ns. Main DDR MEMORY reference takes 100 ns. Waiting for 100 ns. wastes cycles. Adding prefetching etc. is yet another chunk
of transistors.
Sort of for the the same reason it makes GPUs faster - parallelism. You can have multiple CPU cores. Or you can add parallelism to instruction handling by adding branch lookahead - where you basically execute a sequence of instructions in parallel. The deeper the lookahead, the more transistors (exponentially?) need to be added.
Yes, it will, if done right. See [1]. Then see [2], where this is extended to multiplication. Modern multipliers take a lot of transistors but only need a few gate delays before the product appears.
Moore's law was the result of constant development in the lowest level of integrated circuits - lithography and chemistry.
Moore's law made most higher level hardware architecture innovation almost meaningless. Developing new kinds of parallel computers (Gray, Thinking Machines) was dead end when conventional computers made from Intel chips reached the same level in few years without specialized software.
Things have already changed. First specialized Graphics processors and now GPGPU are the first break from the normal. GPGPU's technology is one level up from lithography and silicon chemistry. It's different architecture and different programming paradigm. This will be the first time Intel is not going to shake it off with faster GPU.
We should expect more higher level hardware innovations. Integrating GPU functions into DRAM chips might be the next step.
Considering how often the RAM bottleneck was mentioned in computer performances talks I'm still surprised simple logic / arith instructions didn't hit mainstream RAM modules.
I'm obviously just speculating and handwaving wildly here[1], but ISTM that -- currently -- the limitation here lies mainly in programming languages and semantics. AFAICT all of the non-traditional machine models require radically different programming paradigms[2] and we still aren't quite at that point where gaining more performance is painful enough that the necessary research/innovation will happen. That's assuming that it's even possible. Obviously, any model of computation places some limitations on what can happen and all information transfer (thus computation) is still limited by the speed of light. Some things are just going to remain out of reach forever and not even Quantum Computers are going to help.
[1] As I suppose we all are. C'mon we're talking about predicting the future here.
[2] If you want a practical example, look at the PS/3 Cell processor. I can't claim to have done any 'native' programming for the PS/3, but I've heard (from very clever people that I trust) that it was quite alien and required radically different program structure from what one is used to. And that architecture isn't even that different from 'normal' architectures.
Naive thoughts, compilers could emit ram-local instructions instead of register spill and the likes. Maybe not fancy stuff but I thought there could be a nice class of block swap, or block (inc) that could be generated without too much burden in terms of semantics.
You mentioned "First specialized Graphics processors". I think we can extend things backwards a bit. Earlier machines had specialized sound processors and MPEG decoder chips. As I recall, the early Macs used a 6502 as an I/O controller, and you could get a card for your Apple ][ that would run IBM PC software.
I only mean to extend your timeline. I don't think my observations change your conclusion.
It seems in the article there is a discussion that uses two different definitions for Moore's Law - number of transistors per "space" (and by proxy, size of each transistor) and overall computing power per "space."
When Mr. Moore put his law out there 50+ years ago, perhaps the concept of number/size of transistors was effectively a proxy for computing power, or perhaps even more true, no one saw a difference, or cared to see a difference between the two. Since Mr. Moore is still around, I would love to have his feedback about this- I guess, like Woody Allen's character pulling in Marshall McLuhan in Annie Hall.
Enough of the aside, though: since 1965, much has been learned on the hardware and software sides, industries have grown and shrunk, and we are now able to have debates that - at least somewhat - bifurcate the issue of size/density of hardware from the issue of the somewhat more intangible computing power.
Agreed that he said that in his 1965 paper; research indicates he was asked what would happen in the semiconductor industry (which I see as "the hardware side." He was Director of R&D at Fairchild at the time).
Per several areas I have read, it was after Mr. Moore reviewed his thoughts in 1975 that David House made reference to an 18-month doubling of performance of circuits. This leads to my question about proxy regarding what the thoughts were (or weren't) 10+ years earlier.
Was there any awareness, in 1965, of a difference between transistor count and operating performance, or did this awareness come about later on as industries matured? I tend to think that without any history to define a difference, they would have been viewed as one and the same in 1965. I theorize that at that time Mr. Moore - as a young, 35-36 year old, Director of semiconductor R&D and quite intelligent, undoubtedly - focused on the question as solely about circuits, and not necessarily taking a wider view in his article about overall performance (however performance would have been defined at the time, if it was considered as anything different from transistor size/count/density) when he was asked to write an article about future projections in the semiconductor industry.
You will have to redefine what "consumer equipment" means. I don't see in-home cyro-chilled machines being a thing anytime soon. But perhaps such things will be available at co-location facilities and easily accessed by conventional home machines.
Quantum computing isn't just a faster tech. It's a very different means of answering very specific questions. I cannot see how it would ever be useful for something like a GPU running a game, or a CPU running a macro on a large spreadsheet file. I could see a use for a quantum computing module attached to a computer much like a graphics card, but I cannot see how a quantum processor would do the role of a CPU. Given that, I don't see a market for it in everyday computing.
What in consumer computing needs too much more power than we have now? It seems like the next steps are really battery life and covering more of the plantet with reliable, fast internet service.
54 comments
[ 3.1 ms ] story [ 129 ms ] threadThe potential impact is game-changing. I really wonder how this is going to shape where investments in IT go.
Hence why the explosion in IoT nowadays, that is nothing new. Everyone with some EE background has been playing with microcontrolers since the early 2000.
However we have reached a point where to make such tiny computers, more powerful than any of my PCs at the university, is ridiculously cheap.
A computer like the Arduino used to cost more than 100 euros back in the day, now I can buy one for 5 euros and who cares if it burns.
On the other side of the spectrum we have CPUs like the Nvidia Titan X, which 99% of the computing population can barely make it get out of idle state.
So unless one is an heavy gamer, doing Fintech, VR or AI research there is hardly anything new processors can offer over the existing computing workloads.
So I guess it isn't stop shrinking as such, but also if it will still be economically viable to continue that route until a new computing paradigm emerges (e.g. Quantum or whatever)
Hopefully we'll start to see even more emphasis on optimisation, possibly revived interest in Asm while compilers catch up... and then realise just how efficient software can really be.
The developer mindset needs to change as well. I seldom here people wondering about the sheer computing power of the systems they use.
Many developers also seem to get a kick out of building complex systems (with (most of the time too) many abstraction layers burning cpu cycles) - because they seem to believe building complex things somehow means having control over complexity - but I'm not sure about that.
I wish we had a better, higher level, cross-platform access to SIMD.
https://developer.mozilla.org/en-US/docs/Web/JavaScript/Refe...
The new report embraces these trends, predicting an end to traditional scaling—the shrinking of chip features—by the early 2020’s. But the idea that we’re now facing an end to Moore’s Law “is completely wrong,” Gargini says. ... If a company really wanted to, Gargini says, it could continue to make transistors smaller well into the 2020s, “but it’s more economic to go 3-D. That’s the message we wanted to send.”
This is not to say that I am disagreeing with you on the switch-back-to-2d front, but I don't think we have much further to go on the 2d-density front.
It remains to be seen we still have that 12 years of efficiency available to us after building 3D chips. I can easily imagine that heat distribution would be a real problem.
Given how much of a problem it already is in 2D where the entire die area simply radiates "up and out", I think that head might be the real problem. I don't know how one would build a 3D embedded heat-sink, you know, something like this with the transistors and and connective mesh all around [1]. Maybe it looks like a Menger sponge [2], but that looks tough too! :-)
[1] https://s3.amazonaws.com/s3-blogs.mentor.com/robinbornoff/fi...
[2] https://en.wikipedia.org/wiki/Menger_sponge
The thing is - it's expensive.
But than we can use this to build logic with memory on top ,and get huge bandwidth - and in multicore systems you could 100x performance in some algorithms , with easier programming. But this will be expensive.
But than we could start using those systems, building an ecosystem around them, generate money - and slowly, generation by generation with a moore's law like race, work on building photonics to greatly decrease power consumption - and hence cost.
That's at least the plan in [2].
Also relevant: ST microelectronics is in the final stages of opening a leading edge, commercial photonics fab.
[1]https://www.helpnetsecurity.com/2016/03/11/microfluidic-cool...
[2]http://drum.lib.umd.edu/handle/1903/17153
Now we just need to find a way to build those microchannels stacked at every other layer or so without building fluid junction popping back-pressure! :-)
Or maybe just plan on doubling down on photonics (your #2 suggestion); that certainly makes switching energy (and heat) go way waaay down.
I know if it was that easy we would already be doing it, but I'm hoping somebody knows why. Probably because interfacing the grown diamond to silicon creates interface stress that leads to cracking or...some other reason... :: mutters ::
3D stacking is mostly useful for parts that don't generate much heat. The inner layers have cooling problems. Flash memory, yes; CPUs, no.
Moore's Law was about increasing area density of transistors on a chip. Transistors got smaller and faster. Fabs got more expensive at each shrink, though. For a long time, the cost advantages of the shrink were a win over the increased fab cost. But that's ended. Fab cost ended up dominating the industry. There are only four high-end fab companies left.
The question for years is which limit would dominate - fab cost, heat dissipation, or, ultimately, the size of atoms and electrons. The first two are being reached now. Flash devices are already down to 10-20 significant electrons per storage cell, so there's not much room left there.
Atoms, electrons, and photons are just too big. There's no longer plenty of room at the bottom, as Feynman put it.
Agreed that Moore's law was about increasing density of transistors on a chip - but you can do that in various ways. The article was clear to state, "Moore’s Law, he emphasizes, is simply a prediction about how many transistors can fit in a given area of IC—whether it’s done, as it has been for decades, in a single layer or by stacking multiple layers."
[0] https://en.wikipedia.org/wiki/Adder_(electronics)
[1] https://en.wikipedia.org/wiki/Propagation_delay
Add a ton of transistors to intelligently prefetch and cache will in some cases decrease those 225 CLKs.
A great deal of transistors are added to cache and cache intelligence to get around the terrible latency of DRAM.
The difficulty is in getting all the features you want within the space provided while adhering to the laws of physics.
[1] http://www.slideshare.net/dragonpradeep/carry-look-ahead-add...
Modern CPUs can execute several instructions per clock cycle doing things like this.
There are more ways to speed up your CPU, like identifying instructions that can be executed independently and issue them in parallel, use caches to speed up loading, etc.
1) Smaller circuits (used to?) have less capacitance and smaller voltages. Smaller voltages and capacitance enables higher clock-rate with same power consumption (chips don't melt)
2) Spending more transistors for pipelines and multiple execution units in the same core speeds up the processing. Single instruction takes at least five clock cycles from start to finish. With pipelines it's possible to finish one instruction per cycle. With multiple execution units it's possible to finish more than one instruction per cycle. This all from a single core.
3) Cache. Lots of it, different levels. Accessing external memory is very slow. Main cache reference takes about 1 ns. Main DDR MEMORY reference takes 100 ns. Waiting for 100 ns. wastes cycles. Adding prefetching etc. is yet another chunk of transistors.
[1] https://en.wikipedia.org/wiki/Carry-lookahead_adder [2] https://en.wikipedia.org/wiki/Binary_multiplier
Moore's law made most higher level hardware architecture innovation almost meaningless. Developing new kinds of parallel computers (Gray, Thinking Machines) was dead end when conventional computers made from Intel chips reached the same level in few years without specialized software.
Things have already changed. First specialized Graphics processors and now GPGPU are the first break from the normal. GPGPU's technology is one level up from lithography and silicon chemistry. It's different architecture and different programming paradigm. This will be the first time Intel is not going to shake it off with faster GPU.
We should expect more higher level hardware innovations. Integrating GPU functions into DRAM chips might be the next step.
http://www.micronautomata.com/
They might be missing the boat by not releasing cheap entry level hardware platform, ~$20 ddr3/4 stick.
[1] As I suppose we all are. C'mon we're talking about predicting the future here.
[2] If you want a practical example, look at the PS/3 Cell processor. I can't claim to have done any 'native' programming for the PS/3, but I've heard (from very clever people that I trust) that it was quite alien and required radically different program structure from what one is used to. And that architecture isn't even that different from 'normal' architectures.
http://iram.cs.berkeley.edu/
I only mean to extend your timeline. I don't think my observations change your conclusion.
When Mr. Moore put his law out there 50+ years ago, perhaps the concept of number/size of transistors was effectively a proxy for computing power, or perhaps even more true, no one saw a difference, or cared to see a difference between the two. Since Mr. Moore is still around, I would love to have his feedback about this- I guess, like Woody Allen's character pulling in Marshall McLuhan in Annie Hall.
Enough of the aside, though: since 1965, much has been learned on the hardware and software sides, industries have grown and shrunk, and we are now able to have debates that - at least somewhat - bifurcate the issue of size/density of hardware from the issue of the somewhat more intangible computing power.
Sure, these things are huge today, but we have now in our pockets more power than was available in a Cray super computer from the 80s.