What the article doesn't mention is how the errors are detected -- in a fool proof fashion and cheaply. I can think of error detection schemes that might be cheap to implement but are not foolproof. For instance for an integer multiplication the parity might be cheap to calculate (and without redoing the whole calculation.)
Thus, the error detection algorithm checks the actual parity with the "correct" parity. That of course falls down for multi bit errors.
Razor works by latching a signal twice at different times and comparing the two values; if they differ, the signal must have arrived at the primary latch late which is an error. It specifically detects timing errors which are caused by negative voltage margin, not other types such as soft errors caused by cosmic rays. http://portal.acm.org/citation.cfm?id=956417.956571&coll...
I wouldn't be surprised if Intel's work is similar.
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[ 791 ms ] story [ 2011 ms ] threadThus, the error detection algorithm checks the actual parity with the "correct" parity. That of course falls down for multi bit errors.
Researching the literature a bit:
A different approach (tradeoff precision for power) in GPUs: Energy-precision tradeoffs in mobile Graphics Processing Units (http://iccd.et.tudelft.nl/2008/proceedings/060pool.pdf). Another one (probabilistic chips): http://www.technologyreview.com/energy/20246/.
Edit: Added more detail, formatting.
I wouldn't be surprised if Intel's work is similar.