Up until a couple weeks ago, I was never exposed to processor architecture, let alone the ALU. But, I had purchased the book "Elements of Computing" (nand2tetris.org) which guides the reader through the necessary steps to create a (primitive) operating system, compiler, ALU—from the ground up (starting with a NAND gate). Without the book, I wouldn't have been to appreciate, or understand, this article.
I have degrees in Electrical and Computer Engineering, have designed 4 ALUs and built 3 of those 4. ALUs are interesting, but they're probably one of the most simple components of a CPU. Ignoring look ahead aspects and speculative execution, the instruction decoder is probably the most complex part of a CPU, because it has to decide what inputs to use ( whether register or RAM), what part from which to receive output and where to store the result. An ALU is basically a collection of all of your common mathematical operations you'd expect in the CPU. It just takes inputs and a selector and performs the indicated operation. I designed a (unoptimized) MIPS ALU in Verikog in one evening over a bottle of whiskey (minus division related operations).
I'm glad to see Ken mentioned the Datapoint 2200. It was an interesting machine.
The first generation Datapoint 2200 used a bit-serial dynamic memory, 1 Kb per chip, as it was the most dense form of memory at the time, and the TTL CPU was also bit serial as a result. As you can imagine, performance was pretty slow, which is why Datapoint wanted a byte parallel version, which also used conventional DRAM.
The 2200 used a switch mode power supply, all the way back in 1971, well before it became common. In fact, the Apple II was noted for being revolutionary in 1976 for using a switching power supply.
The CRT was refreshed using what they called "diddle scan" (IIRC). Rather than having a continuous sweep like most CRTs, it actually scanned the dot matrix for each character, one at a time. So internally it would park the X,Y CRT offsets at a fixed point in each character, and another circuit would then add x,y offsets to sweep the beam across that little neighborhood. Then the X,Y offset was moved to the next character location. This fit in well with the serial memory of the first generation machine, as doing it conventionally would require fetching the display bytes once for each scan row, instead of once for each character.
The machine didn't have any boot ROM. Instead, an fsm would turn on the first cassette drive and read in the first 32 bytes (?) from the tape, which then gave it enough smarts to take over and read the rest of the OS into the machine.
By the time TI and Intel had a chip ready, Datapoint had already redesigned the system using TTL, which was faster than the IC versions. The next generation CPU was also discrete TTL and was advanced far beyond Intel's next part, the 8080.
Thanks for the Datapoint 2200 details. For such an influential machine, it seems almost forgotten now.
By the way, I took die photos and analyzed the Intel shift-register memory you mention: http://www.righto.com/2014/12/inside-intel-1405-die-photos-o...
An interesting thing about shift-register memory is it performs well if you do sequential access, but if you access anything out of order, you need to wait for the bits to go all the way around, up to 0.5ms.
I worked for Datapoint from 1975 to 1977 as a technician in board test and repair. I started out working on power supplies, later moved to mod/demod boards (for the tape drives), then to processor boards.
I only repaired a few of the old serial processors, these were boards sent in from existing customers for repair. The production boards were the TTL boards for 2200 and 5500.
The 2200 boards used a pair of 74181 ALU chips and a pair of 7489 RAM chips for the registers. They had 121 total ICs, ran at 8MHz, and instruction decoding was performed with mostly SSI chips.
The 5500 boards had 131 ICs, the ALU and registers were 74S series chips and ran at 20 MHz. Instruction decoding was done by microprogrammed ROMs. The instruction set was very similar to the Z80.
While the 8008 executed the 2200 instruction set, later chips made by Intel and Zilog changed the register numbers at Datapoint's request so as to prevent them from running Datapoint's code which represented a major investment for the company.
On Datapoint processors, a register/register load instruction was (in octal) 3 dst src. The later chips changed this to 1 dst src, with the instruction type (high 2 bits) having the high bit inverted from Datapoint.
Dst and src were similarly changed, Datapoint having A=0, B=1, ...,(HL)=7 and the later chips having A=7, B=0, ..., (HL)=6.
Were these early ICs prototyped with discrete components on breadboards? Simulated with programs on mainframes? I assume most of the drafting for the masking was done manually.
Just curious how the design process worked at this stage in the game.
They simulated the 8008's logic on a PDP-8 and a timeshare computer. The drafting was done manually. Each layer of the chip was cut by hand from a big sheet of red plastic film known as Rubylith. That is, every transistor and every wire was cut out with an X-acto knife. These sheets were then photographically reduced for the chip masks. If you visit the Computer History Museum, there's a Rubylith on the wall from a memory chip.
> unlike most 1970's microprocessors, the 8008 uses a complex carry-lookahead circuit to increase its performance.
And around 1835 (some 180 years ago!), Charles Babbage created a design for a fully mechanical "Analytical Engine" with the complex "Anticipating Carriage."
"This was a most important step in the evolution of the Analytical Engine, for" "there gradually emerged the notion of a central processing section in which the various arithmetical functions were to be carried out, distinct from the area where the numbers were stored when not being manipulated. The central processing unit Babbage later came to call the "Mill," and the other number columns he called collectively the "Store," this fundamental distinction of course still exists in current computer." Not to mention that he also designed a printer(!) and the punched card readers(!) to control his machine.
Babbage was proud of his "Anticipating Carriage" mechanism, a huge change compared to his design of "Difference Engine" which had a serial carry which can be here seen moving from the position to the position (Babbage designed the engines to calculate with a lot of decimal places):
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[ 2.8 ms ] story [ 19.2 ms ] threadUp until a couple weeks ago, I was never exposed to processor architecture, let alone the ALU. But, I had purchased the book "Elements of Computing" (nand2tetris.org) which guides the reader through the necessary steps to create a (primitive) operating system, compiler, ALU—from the ground up (starting with a NAND gate). Without the book, I wouldn't have been to appreciate, or understand, this article.
The first generation Datapoint 2200 used a bit-serial dynamic memory, 1 Kb per chip, as it was the most dense form of memory at the time, and the TTL CPU was also bit serial as a result. As you can imagine, performance was pretty slow, which is why Datapoint wanted a byte parallel version, which also used conventional DRAM.
The 2200 used a switch mode power supply, all the way back in 1971, well before it became common. In fact, the Apple II was noted for being revolutionary in 1976 for using a switching power supply.
The CRT was refreshed using what they called "diddle scan" (IIRC). Rather than having a continuous sweep like most CRTs, it actually scanned the dot matrix for each character, one at a time. So internally it would park the X,Y CRT offsets at a fixed point in each character, and another circuit would then add x,y offsets to sweep the beam across that little neighborhood. Then the X,Y offset was moved to the next character location. This fit in well with the serial memory of the first generation machine, as doing it conventionally would require fetching the display bytes once for each scan row, instead of once for each character.
The machine didn't have any boot ROM. Instead, an fsm would turn on the first cassette drive and read in the first 32 bytes (?) from the tape, which then gave it enough smarts to take over and read the rest of the OS into the machine.
By the time TI and Intel had a chip ready, Datapoint had already redesigned the system using TTL, which was faster than the IC versions. The next generation CPU was also discrete TTL and was advanced far beyond Intel's next part, the 8080.
By the way, I took die photos and analyzed the Intel shift-register memory you mention: http://www.righto.com/2014/12/inside-intel-1405-die-photos-o... An interesting thing about shift-register memory is it performs well if you do sequential access, but if you access anything out of order, you need to wait for the bits to go all the way around, up to 0.5ms.
I only repaired a few of the old serial processors, these were boards sent in from existing customers for repair. The production boards were the TTL boards for 2200 and 5500.
The 2200 boards used a pair of 74181 ALU chips and a pair of 7489 RAM chips for the registers. They had 121 total ICs, ran at 8MHz, and instruction decoding was performed with mostly SSI chips.
The 5500 boards had 131 ICs, the ALU and registers were 74S series chips and ran at 20 MHz. Instruction decoding was done by microprogrammed ROMs. The instruction set was very similar to the Z80.
While the 8008 executed the 2200 instruction set, later chips made by Intel and Zilog changed the register numbers at Datapoint's request so as to prevent them from running Datapoint's code which represented a major investment for the company.
On Datapoint processors, a register/register load instruction was (in octal) 3 dst src. The later chips changed this to 1 dst src, with the instruction type (high 2 bits) having the high bit inverted from Datapoint.
Dst and src were similarly changed, Datapoint having A=0, B=1, ...,(HL)=7 and the later chips having A=7, B=0, ..., (HL)=6.
Just curious how the design process worked at this stage in the game.
See the very interesting 8008 oral history for more information: http://archive.computerhistory.org/resources/access/text/201...
And around 1835 (some 180 years ago!), Charles Babbage created a design for a fully mechanical "Analytical Engine" with the complex "Anticipating Carriage."
http://robroy.dyndns.info/collier/ch3.html
"This was a most important step in the evolution of the Analytical Engine, for" "there gradually emerged the notion of a central processing section in which the various arithmetical functions were to be carried out, distinct from the area where the numbers were stored when not being manipulated. The central processing unit Babbage later came to call the "Mill," and the other number columns he called collectively the "Store," this fundamental distinction of course still exists in current computer." Not to mention that he also designed a printer(!) and the punched card readers(!) to control his machine.
The video that demonstrates the mechanism:
https://www.youtube.com/watch?v=B2EDE8Srdcw
It was made by the author of a beautiful comics about Lovelace and Babbage:
https://en.wikipedia.org/wiki/The_Thrilling_Adventures_of_Lo...
Babbage was proud of his "Anticipating Carriage" mechanism, a huge change compared to his design of "Difference Engine" which had a serial carry which can be here seen moving from the position to the position (Babbage designed the engines to calculate with a lot of decimal places):
https://www.youtube.com/watch?v=BlbQsKpq3Ak&t=15m36s