Agile Paging for Efficient Memory Virtualization [pdf] (research.cs.wisc.edu) 37 points by ingve 9y ago ↗ HN
[–] crave_ 9y ago ↗ "Even the TLBs in the recent Intel Skylake processor architecture, cover only 9% of a 256 GB memory."Isn't that sort of a lot since the TLB is per context anyways? [–] monocasa 9y ago ↗ The TLB is shared for the whole system. They added ASIDs so you can keep multiple contexts around without flushing the TLB.It's still not a great comparison though since TLBs are essentially cache. You only need to keep your working set in them.
[–] monocasa 9y ago ↗ The TLB is shared for the whole system. They added ASIDs so you can keep multiple contexts around without flushing the TLB.It's still not a great comparison though since TLBs are essentially cache. You only need to keep your working set in them.
2 comments
[ 5.6 ms ] story [ 19.8 ms ] threadIsn't that sort of a lot since the TLB is per context anyways?
It's still not a great comparison though since TLBs are essentially cache. You only need to keep your working set in them.