My info is several years old, but it was super frustrating, because both amd and cavium claimed to be selling ARM servers, and I was stoked to sell arm-based VPSs, and I even had an ARM/linux friend on hand to help out... but nobody would sell me any. Maybe they were only selling in lots over 100 or something? Maybe my sales contacts weren't good enough.
It would be interesting to hear from someone who has taken delivery of one of these units.
You've been able to buy Cavium ThunderX (v1) for a long time. I wouldn't recommend them because of poor single thread performance and the fact that ThunderX2 is nearly there, but for example: https://www.avantek.co.uk/arm-server-h270-t70/
Qualcomm Amberwing is also available to buy, although at a somewhat eye-watering price.
curious - why parallel build with about 32 compiler (ie. cpu heavy) instances with total 93% user cpu load (and no wait, etc) shows individual processes at 48% cpu max on that machine (which i suppose is at least 24 cores and probably 48)? In that situation on Lintel the top processes are usually shown as close to 100% cpu. Is it just a quirk of system accounting on those ARMs? Or do all these compiler processes contend on something (like for example may be memory bus)?
It is fairly unlikely to saturate 46 CPUs with a kernel compile. However it's probably much better off than if it were C++ source. Yes, I'd absolutely expect memory contention when it's not I/O bound.
IMHO it’s less about Skylake being special and more about the previous generations having fairly small improvements over their predecessors.
Broadwell was never a huge leap for general purpose server performance. At least it didn’t get perceived as such. It seemed to concentrate on being good at the low power end to compete with ARM and more virtualization features iirc.
For some, rather like phones these days: they’re good enough not to need a refresh as often as they might have been.
For others Skylake is the first real jump / change in performance (the cache hierarchy and core interconnect topology changes are particularly interesting to me).
For yet others, they delayed refreshing for longer than they used to: “we might as well wait until the next release now”. And once Skylake was out in all its thousand-different-sku glory they bought it.
Broadwell for servers was noteworthy for the Xeon-D line, which has some neat performance characteristics in a tiny power envelope, but it was very targeted at the laptop market - hell, there were only 6 models of desktop processors, compared to 32 laptop models, or 50+ server processors (half of which are the Xeon-D line, and the other half were so delayed that the E3 Skylakes landed before the E5 Broadwells did, and then the E5 Skylake equivalents got delayed forever, presumably in part to finally also support the socketable Xeon Phis Intel wanted so much)
As someone who waited for the new server CPUs, the microarchitecture made a few changes that should substantially improve its performance for data-intensive workloads:
- 6 memory channels (instead of 4)
- new CPU cache architecture that should show big gains for things like databases
- new vector ISA (AVX-512) that is significantly more useful than AVX2, in addition to being twice as wide
The first two should be instant wins for things like databases. AVX-512 isn't going to be used in much software yet but it is arguably the first broadly usable vector ISA that Intel has produced. This should enable some significant performance gains in the future as code is rewritten to take advantage of it. (Not idle speculation on the latter, we're queued up to get some of this hardware for exactly this purpose. Previously vectorizing wasn't worth the effort outside of narrow, special cases but AVX-512 appears to change that.)
Have you found benchmarks yet for the second point (DB perf)? I assume by "new cache architecture" you're referring to the switch from a ring to a mesh for L3, which was almost necessitated by having more cores in SKL. But at the same time they reduced associativity from 8 to 4 (worse) and made L1-L3 non-inclusive (unsure of the effects yet). They did expand L2 a bit though.
No benchmarks yet (and it will be difficult to isolate that effect).
The cache structure more closely mirrors the data locality intrinsic in recent high-performance database engines, which don't share data pages across cores and which now commonly use page sizes (256k) that don't fit in L2. The increase in cache size from 256k to 1M is particularly important because it allows you to store multiple pages in L2 which should make a number of multi-page and complex query on single page operations significantly more efficient. Should be great for join kernels. Similarly, the non-inclusive and smaller shared L3 makes more sense in that the amount of state shared across cores is actually pretty small. In short, it redistributes cache resources in a way that is very useful to the way database engines are currently designed.
Is Epyc really going to make any big impact on the global server market? Call me old-fashioned, but I just can't imagine enterprises moving to Epyc any time soon. Intel has built a really powerful brand with Xeon over the years.
People who buy a lot of servers look more carefully into their purchases than consumers. Brand reputation does matter, but if you can save 10% by switching to another quality brand, it's a no brainer. Of course you'll want to do a evaluation run for a few months.
There are going to be small shops for which the familiarity of Xeon will be enough to keep them in the same pattern. If 10% of your costs are just a few weeks or months of engineer time, and you only have an engineer or two to spare, it's a big risk and expense to figure out the different costs and to do that evaluation run. There are a lot of shops like that.
There are not as many huge enterprises, but they are a huge amount of the market in terms of volume, and at those scales a 1% savings is worth years of engineering expenses, and you can bet that they will be doing the studies and choosing the most cost-effective option regardless of previous decisions.
What percentage do Microsoft Azure, Google Cloud, AWS, OVH, Tencent Cloud, AliCloud combined for Intel's DC Market? My guess is that they are over 50%.
And most of these Skylake order were placed well in advance, when they / the market didnt even have time to evaluate EPYC.
I do think they will move to EPYC in some form, just to keep Intel's price in check. After all EPYC offers much more value.
To hell with skylake, I can't wait to build dual eypc servers. I learned about the power of heavy parallelization while sysadmin'ing at a genetics lab, and ever since building a quad CPU opteron system I've wanted more of that kind of server. This time though I only need two CPUs to get 64 cores!
24 comments
[ 1.7 ms ] story [ 56.6 ms ] threadIt would be interesting to hear from someone who has taken delivery of one of these units.
Qualcomm Amberwing is also available to buy, although at a somewhat eye-watering price.
Edit: Teaser picture: https://rwmj.wordpress.com/2017/11/20/make-j46-kernel-builds... As usual because of NDAs I'm not allowed to publish benchmarks.
Broadwell was never a huge leap for general purpose server performance. At least it didn’t get perceived as such. It seemed to concentrate on being good at the low power end to compete with ARM and more virtualization features iirc.
For some, rather like phones these days: they’re good enough not to need a refresh as often as they might have been.
For others Skylake is the first real jump / change in performance (the cache hierarchy and core interconnect topology changes are particularly interesting to me).
For yet others, they delayed refreshing for longer than they used to: “we might as well wait until the next release now”. And once Skylake was out in all its thousand-different-sku glory they bought it.
Edit: typo
- 6 memory channels (instead of 4)
- new CPU cache architecture that should show big gains for things like databases
- new vector ISA (AVX-512) that is significantly more useful than AVX2, in addition to being twice as wide
The first two should be instant wins for things like databases. AVX-512 isn't going to be used in much software yet but it is arguably the first broadly usable vector ISA that Intel has produced. This should enable some significant performance gains in the future as code is rewritten to take advantage of it. (Not idle speculation on the latter, we're queued up to get some of this hardware for exactly this purpose. Previously vectorizing wasn't worth the effort outside of narrow, special cases but AVX-512 appears to change that.)
The cache structure more closely mirrors the data locality intrinsic in recent high-performance database engines, which don't share data pages across cores and which now commonly use page sizes (256k) that don't fit in L2. The increase in cache size from 256k to 1M is particularly important because it allows you to store multiple pages in L2 which should make a number of multi-page and complex query on single page operations significantly more efficient. Should be great for join kernels. Similarly, the non-inclusive and smaller shared L3 makes more sense in that the amount of state shared across cores is actually pretty small. In short, it redistributes cache resources in a way that is very useful to the way database engines are currently designed.
There are not as many huge enterprises, but they are a huge amount of the market in terms of volume, and at those scales a 1% savings is worth years of engineering expenses, and you can bet that they will be doing the studies and choosing the most cost-effective option regardless of previous decisions.
And most of these Skylake order were placed well in advance, when they / the market didnt even have time to evaluate EPYC.
I do think they will move to EPYC in some form, just to keep Intel's price in check. After all EPYC offers much more value.
"Microsoft Announces Azure VMs with Dual 32-core AMD EPYC CPUs" - https://www.anandtech.com/show/12116/amd-and-microsoft-annou...
Wouldn't be surprised to see an equivalent AWS announcement soon, either.