Disagree. mmWave on generic CMOS is very impressive. Sure, you can take a SiGe or III-V front end, and marry that up to CMOS back ends, but then you don’t meet the price point. Put in an FPGA, then you are way over price.
The baseband bandwidth for FMCW RADAR is not that much, so they are able to pull this off with a DSP. It’s the RF integration that impressed me. I’m presently using some ADI SiGe mmWave ICs (impressive themselves), and those are close to $300 for the TX/RX pair, and that’s only the RF to analog baseband. The TI part is $55 for a fully integrated chip. Just need a PCB/antenna and supply regulators.
The novel part is that the whole radar front end is also integrated, including the RF PAs. Literally just one chip for everything directly connected to the antennas.
I have programmed for the same c674x chips they mention as doing machine learning ... Let's just say the have a mere fraction of the FLOPs that a nvidia GPU or other "AI" processor would have.
Granted, good machine learning is not all about compute power, and you can certainly do interesting things with less power. But this is not bleeding edge deep learning for sure :)
On the other hand, TI is a company you can actually count on to work with you to be able to build a product that can be verified to be dependable, in a mission-critical, hard real time sense. TI open sources most of the software stack.
NVIDIA, well, not so much. I've run into serious issues with their binary blob drivers and their engineers have a rather DGAF attitude about the whole thing. Secrecy and bluster are the name of the game. Torvalds' opinion on the matter rings true.
TI just seems friendlier and less cutthroat. Their support of the BeagleBoard etc is telling.
Yeah, you don't want to do AI in DSP, but signal processing yes.
There's a lot of work between reflecting radio signals and having a "radar image" that can be fed to AI systems, and that seems to be the main target of the dsp.
Would it be plausible to train slowly on a DSP, if the data is also being collected slowly, at the edge?
By the time you have a reasonable dataset, you've also had a reasonable amount of training... of course, with only a little training on the complete dataset.
Depends on your model - in the majority of cases training is a separate act from using the model, and just because you trained it doesn't mean it's well fitted. You end up caring about training speed because you don't know how many training runs you may have to do, grumpily fiddling with the model and hyperparameters after each training session trying to get a good model. Technically possible but probably not practical
Indeed, it is a shame that so harmful to the industry company like an NVIDIA became a leader in Machine Learning. Hopefully it will change soon enough.
Also good about TI is they are far more willing to have a long term commitment to a particular chip or other component which is a must when you're designing something that you want to market for at least a couple of years.
There is nothing more irritating than to finalize a design for manufacturing and being hit with an EOL'd part with some ridiculously short deadline.
You end up with having to choose between to really bad choices: stock up as many parts as you can risking ending up with unused inventory (and still a fair chance of running out on the other end) and redesigning the product.
I had to register to comment about TI "quality" and friendliness ;-).
Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktdma will hang if you will use chained descriptors but you will not find it in silicon errata. TI response was - "just don't use it" and refused to verify it on their side.
The ISA of c66x DSP is just stupid - you have quad SP multiply but only double SP addition - forming registers back and forth in quads will result in MV instructions often (because compiler is not so smart).
There are no real vector registers, "vector" instructions take 4 or 2 32bit registers.
Want to compute power of individual complex int16 in a vector ? You are out of luck - DDOTP4H will add everything together.
There is even no way to utilize their multipliers fully since load&store is 2x64 bit, while multiplier can perform 8 SP multiplies per cycle.
Moreover memory access to L2 is so slow that you will wait in memory stalls (there is no HW prefetch from L2 to L1D cache) and L1 SRAM is way to small to do anything serious (32 kB).
After trying other DSPs, like CevaXC or VSPA, TI looks like poor joke. Their C7000 that supposed to address some of those problems is long overdue and will be well underpowered comparing to recent Ceva DSPs or NXP VSPA.
Just what I want - millimeter wave radar blasting at me everywhere I go. Sure, it's non-ionizing radiation, but where are the long term safety studies?
They are adequately shielded, but also have 1 kW resonating inside. They have enough to meet the OSHA standard of 1 mW/cm^2.
The chip in question only emits 20 mW, and coupled into a 10 dB gain antenna, the EIRP is still only a few 100 mW. Now spread that over a few 1000 cm^2, and it’s not much at all.
For a fun experiment, put your phone in a microwave. Notice the WiFi bars go to zero, but the cellular bars don’t change (much).
21 CFR 1030.10 limits radiation from a microwave to 5 milliwats per square centimeter (at a distance of 2 inches). For an average-sized microwave that's over 8 watts from the front of the device. Again that's a maximum, but it's possible. TI's devices are customizable but an example on the site shows total power draw of 1.4 watts.
Since each photon doesn't have enough power to damage your molecules, non-ionizing radiation just heats you up when it gets absorbed. Since you're not getting enough heat to cook you, or even make you slightly uncomfortable, that is the extent of the effect.
We need to understand that as platforms start offering different services which serve different purposes, they start spawning platforms which become independent of their predecessors.
They may be new buzzwords, but it's important to differentiate them so that the use cases and end users they are targeting become more narrow and specific.
Just wondering, the last time I touched DSPs was in EE school. How can I keep up interest in the field if I am working in a seperate field? Any good resources and projects worth undertaking?
30 comments
[ 5.1 ms ] story [ 117 ms ] threadTypically, the dsp or fpga is used to handle the time critical pieces, i.e. generating RF, and the pc is there to command and collect data.
There are a variety of vendors you can choose from for this type of setup. From SoC to PCIe fpga for a server, all depends on your applicatio.
The application to the automotive sector might be novel.
The baseband bandwidth for FMCW RADAR is not that much, so they are able to pull this off with a DSP. It’s the RF integration that impressed me. I’m presently using some ADI SiGe mmWave ICs (impressive themselves), and those are close to $300 for the TX/RX pair, and that’s only the RF to analog baseband. The TI part is $55 for a fully integrated chip. Just need a PCB/antenna and supply regulators.
Short white paper here:
http://www.ti.com/lit/an/swra592/swra592.pdf
I'm curious what kind of Rx sensitivity they can get for the HF range.
Granted, good machine learning is not all about compute power, and you can certainly do interesting things with less power. But this is not bleeding edge deep learning for sure :)
On the other hand, TI is a company you can actually count on to work with you to be able to build a product that can be verified to be dependable, in a mission-critical, hard real time sense. TI open sources most of the software stack.
NVIDIA, well, not so much. I've run into serious issues with their binary blob drivers and their engineers have a rather DGAF attitude about the whole thing. Secrecy and bluster are the name of the game. Torvalds' opinion on the matter rings true.
TI just seems friendlier and less cutthroat. Their support of the BeagleBoard etc is telling.
There's a lot of work between reflecting radio signals and having a "radar image" that can be fed to AI systems, and that seems to be the main target of the dsp.
I too have nothing but great things to say about TI.
By the time you have a reasonable dataset, you've also had a reasonable amount of training... of course, with only a little training on the complete dataset.
There is nothing more irritating than to finalize a design for manufacturing and being hit with an EOL'd part with some ridiculously short deadline.
You end up with having to choose between to really bad choices: stock up as many parts as you can risking ending up with unused inventory (and still a fair chance of running out on the other end) and redesigning the product.
Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktdma will hang if you will use chained descriptors but you will not find it in silicon errata. TI response was - "just don't use it" and refused to verify it on their side.
The ISA of c66x DSP is just stupid - you have quad SP multiply but only double SP addition - forming registers back and forth in quads will result in MV instructions often (because compiler is not so smart). There are no real vector registers, "vector" instructions take 4 or 2 32bit registers.
Want to compute power of individual complex int16 in a vector ? You are out of luck - DDOTP4H will add everything together.
There is even no way to utilize their multipliers fully since load&store is 2x64 bit, while multiplier can perform 8 SP multiplies per cycle.
Moreover memory access to L2 is so slow that you will wait in memory stalls (there is no HW prefetch from L2 to L1D cache) and L1 SRAM is way to small to do anything serious (32 kB).
After trying other DSPs, like CevaXC or VSPA, TI looks like poor joke. Their C7000 that supposed to address some of those problems is long overdue and will be well underpowered comparing to recent Ceva DSPs or NXP VSPA.
The chip in question only emits 20 mW, and coupled into a 10 dB gain antenna, the EIRP is still only a few 100 mW. Now spread that over a few 1000 cm^2, and it’s not much at all.
For a fun experiment, put your phone in a microwave. Notice the WiFi bars go to zero, but the cellular bars don’t change (much).
And neither will you.
They may be new buzzwords, but it's important to differentiate them so that the use cases and end users they are targeting become more narrow and specific.