Monolithic 3D is also sometimes called "sequential 3D". In essence, instead of current 3D integration which fabricates several 2D chips, then thins them, adds TSVs, aligns and then finally bonds them, Monolithic 3D makes 3D chips layer by layer.
The advantages are that it can have extremely dense chip to chip connections, as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance (can be as much as ~50fF!!).
The disadvantages are that copper interconnects melt above ~400 degrees celsius, and we are around ~1200 degrees celsius to make transistors. There are a few ways around this but they usually result in crummier transistors.
Yes, although this can be an extra challenge in monolithic 3D because it often involves oxide layers and thin silicon * between transistor layers, which makes the heat conduction much worse.
I don't think anyone's tried but there can be all sorts of "fun" issues, e.g. directly putting many high-k oxides onto transistors results in fermi level pinning.
EDIT: I did look at this idea some time back and I believe AMD even has a patent on it (though I might be mistaken), it's possible, but might cause unexpected issues.
So the issue is that stuff like this (e.g. Fermi level pinning induced by HfO2 directly on Si without a metal gate) tends to be industry "secret" stuff and tends to not be in textbooks. You'll usually catch this info from talking to process engineers and reading papers.
From what I understand, another disadvantage of monolithic 3D are the yield implications.
When you fabricate several 2D chips and then integrate them, it allows you to test those 2D chips for errors separately before the integration, which should give you better yields overall.
From the various articles in the thread it seems that these are single die computers, think something like bringing the cache on die from back in the day.
As a computer architect, I’m really curious what their practical capabilities will be for this process. There’s definitely a market for low volume / high performance chips if they can develop something interesting (ie mask costs similar to 90nm but performance closer to 7nm).
Wrapping around sides isn't easy because chips are cut from a single large wafer pretty late in manufacturing. The sides aren't exposed until the end.
Besides, it won't help much. Usually when people want to shrink chips, it's often because shorter links. This means lower latency (ie faster) and lower heat loss. Wrapping or stacking doesn't help those.
It's a manufacturing limitation. Integrated circuits are nearly universally built via photolithography [1], which only makes flat 2D layers. Stacking many, many layers for 3D circuits is feasible; building layers on different sides of an object would require re-engineering every part of the process, including the use of large silicon wafers, for a much more complex process with negligible (if any) benefit.
22 comments
[ 3.4 ms ] story [ 51.6 ms ] threadThe advantages are that it can have extremely dense chip to chip connections, as much as ~10,000X as dense as TSVs (literally) and no ESD diode capacitance (can be as much as ~50fF!!).
The disadvantages are that copper interconnects melt above ~400 degrees celsius, and we are around ~1200 degrees celsius to make transistors. There are a few ways around this but they usually result in crummier transistors.
*due to violation of Fourier theory of heat.
EDIT: I did look at this idea some time back and I believe AMD even has a patent on it (though I might be mistaken), it's possible, but might cause unexpected issues.
I'm a physics major, but haven't gotten to do much semiconductor coursework yet.
When you fabricate several 2D chips and then integrate them, it allows you to test those 2D chips for errors separately before the integration, which should give you better yields overall.
Besides, it won't help much. Usually when people want to shrink chips, it's often because shorter links. This means lower latency (ie faster) and lower heat loss. Wrapping or stacking doesn't help those.
[1] https://en.wikipedia.org/wiki/Photolithography#Basic_procedu...
edit: kragormonkey beat me to it!
See also, the DoD trusted foundry program
https://www.google.com/search?q=dod+trusted+foundry+program&...
You can find many good books, especially from 80th-90th
https://www.top500.org/news/darpa-picks-research-teams-for-p...