[–] ncmncm 7y ago ↗ I have long wondered about systolic arrays. It used to be hard to find out much about them because they were almost always military. [–] jeschiefer 7y ago ↗ Everything old is new again. Popular High-Level Synthesis compilers like to generate systolic arrays, because they map so well to FPGA architecture. [–] pkaye 7y ago ↗ I believe the Google TPUs using systolic array architecture. [–] amelius 7y ago ↗ It seems that systolic arrays trade flexibility for performance. This makes me wonder in what way TPUs are less flexible than GPUs. [–] convolvatron 7y ago ↗ HT did work on a systolic machine with Intel https://en.wikipedia.org/wiki/IWarpfrom what I can recall, there was never a magic compiler to lay out arbitrary problems on the 2d mesh. there was a 2d image processing framework that (I think) presented a simd-like kernel model.
[–] jeschiefer 7y ago ↗ Everything old is new again. Popular High-Level Synthesis compilers like to generate systolic arrays, because they map so well to FPGA architecture.
[–] pkaye 7y ago ↗ I believe the Google TPUs using systolic array architecture. [–] amelius 7y ago ↗ It seems that systolic arrays trade flexibility for performance. This makes me wonder in what way TPUs are less flexible than GPUs.
[–] amelius 7y ago ↗ It seems that systolic arrays trade flexibility for performance. This makes me wonder in what way TPUs are less flexible than GPUs.
[–] convolvatron 7y ago ↗ HT did work on a systolic machine with Intel https://en.wikipedia.org/wiki/IWarpfrom what I can recall, there was never a magic compiler to lay out arbitrary problems on the 2d mesh. there was a 2d image processing framework that (I think) presented a simd-like kernel model.
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[ 3.0 ms ] story [ 17.8 ms ] threadfrom what I can recall, there was never a magic compiler to lay out arbitrary problems on the 2d mesh. there was a 2d image processing framework that (I think) presented a simd-like kernel model.