I've heard that diffusion can disrupt work of diodes and transistors by corrupting p-n junctions. Don't know what time is required for diffusion to destroy p-n junction and couldn't find an answer via Google.
Yes, that is a major factor in aging of chips. But giving a number for this is very difficult, as it varies on a lot of parameters. Quite a lot depends on the process the chip was manufactured with. Older processes with larger feature sizes usually are less affected than modern processes with smaller structures. But almost all details of processes are confidential and available under NDA only, so not openly published. Also, it depends on the concrete designs. That is, why the carrier migration is simulated as part of the modern design process.
Of course, also the operation conditions play a role. The hotter the chip is and the higher the operation voltage, the quicker the diffusion happens.
There are many effects that contribute to semiconductor aging. Thermal stress and diffusion, as you and the child comment suggested, are definitely part of it. There is also electromigration, which can cause the interconnect to fail. In advanced nodes there are effects related to the magnitude of the electric field and the various material interfaceds, such as hot-carrier injection (HCI). Here's an article which gives explanation of a few aging effects:
As others have noted, yes. It definitely impacts things. Semiconductor evaluation includes a significant time spent on long life expectancy (look up HTOL, or BHAST testing). HTOL and BHAST aren't just to evaluate for thermal stress (in fact, generally, there's ramp rates associated with the temperature changes to make sure you don't thermally shock something). They do it because diffusion, electromigration, etc, get much worse at higher bias voltages and high temperatures.
This was significantly less of an issue on older stuff (or on stuff that is run on really large nodes, which tends to be older), since you have to diffuse a LOT more material to actually cause problems compared to the 7nm stuff today.
I'd read a discussion some time ago that guessed it was the adipic acid present in some types of polyurethane foam. Polyethylene foam doesn't seem to have the issue.
So I was given a binder of 6502s and a bunch of EEPROMS as a kid. I’m pretty sure they are still sitting in that black foam in a barn. So how does the foam rot the pins?
Collects moisture and keeps it right there by the pin. There might well be some chemical breakdown too, the older foam loses its spring so must be changing composition as it ages.
Cringed at the wooden block, older ICs like that are a lot more sensitive to ESD damage than modern ones, he should have covered that end of the wooden block with foil.
Cool that someone has found a working 6502 from the first batches though! I wonder how many are left out there...
You sure about that? Maybe 6502's are old enough before proper ESD protection circuitry became mainstream, but generally smaller nodes are a lot more sensitive to ESD damage than the ancient stuff since the size of features back then just was so much bigger.
There's a reason why HBM ESD limits have gone down over time... just because it's physically impossible to protect against a certain level of ESD when you're running ultra high speed circuits.
That's a good point, I think I'd just heard that a long time ago and not really thought about it but with much larger features it should actually be more resilient.
Had a single board Synertek kit, 6502 based with 2112 RAMs... in 1979? Had to do the math, didn't realize it was that "late" in the 6502 history.
Such a fun fun processor to work on at age 12... and I've always been grateful to have learned programming from the ground up. Always feel closer to the metal since I am aware how many layers there are under whatever I'm working in.
There's nothing wrong with using a screwdriver to remove a chip like this, provided it's done carefully. With that said, I'd probably have used a guitar pick.
Some of the chip pullers are excessively violent and apply force to both ends of the chip. If the centre pins of the chip are stuck, the chip may end up being snapped in two.
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[ 3.1 ms ] story [ 77.1 ms ] threadCapacitor ageing is pcb dielectric leakage. Coils rust. Chips? Sealed, layered devices?
Thermal stress, I could believe
https://spectrum.ieee.org/semiconductors/processors/transist...
This was significantly less of an issue on older stuff (or on stuff that is run on really large nodes, which tends to be older), since you have to diffuse a LOT more material to actually cause problems compared to the 7nm stuff today.
Cool that someone has found a working 6502 from the first batches though! I wonder how many are left out there...
There's a reason why HBM ESD limits have gone down over time... just because it's physically impossible to protect against a certain level of ESD when you're running ultra high speed circuits.
I'm not sure where CBM/MOS's HMOS process (used for -- IIRC -- the SID and VIC) fits in.
Such a fun fun processor to work on at age 12... and I've always been grateful to have learned programming from the ground up. Always feel closer to the metal since I am aware how many layers there are under whatever I'm working in.
You often see correction wires on early PCBs but a breadboard - that's some hacking in my definition right there.
First stating how rare these white 6502s are, then use brute-force methods to remove the chips off the board.
He could have at least used a proper chip-puller. Seeing those bent pins on 40+-year-old ROMs breaks my heart :(.
Some of the chip pullers are excessively violent and apply force to both ends of the chip. If the centre pins of the chip are stuck, the chip may end up being snapped in two.