What makes registers and L1 cache so much more expensive than L2/L3/RAM? 1 points by gtirloni 5y ago ↗ HN
[–] phonethrowaway 5y ago ↗ SRAM?What do you mean by expensive?Size vs speed? [–] phonethrowaway 5y ago ↗ L1 cache is optimized for speed. You can't make a large L1 cache... the access is too frequent meaning more bandwidth is needed. L1 has many parallel pipelines vs L2 or 3 which are larger caches, respectively, with less pipelining, respectively. [–] phonethrowaway 5y ago ↗ Bigger size means more latency. L1 needs to be fast due to frequent access. Is that what you mean by expensive?
[–] phonethrowaway 5y ago ↗ L1 cache is optimized for speed. You can't make a large L1 cache... the access is too frequent meaning more bandwidth is needed. L1 has many parallel pipelines vs L2 or 3 which are larger caches, respectively, with less pipelining, respectively. [–] phonethrowaway 5y ago ↗ Bigger size means more latency. L1 needs to be fast due to frequent access. Is that what you mean by expensive?
[–] phonethrowaway 5y ago ↗ Bigger size means more latency. L1 needs to be fast due to frequent access. Is that what you mean by expensive?
3 comments
[ 3.4 ms ] story [ 14.4 ms ] threadWhat do you mean by expensive?
Size vs speed?