I almost pity Intel for having to maintain old x86 memory model decisions they made over 35 years ago.
They tried to get rid of strictly ordering almost all load/stores with Itanium, but they bungled that product so hard. Now switching ISAs would look like a weakness no matter what they do.
No CPU [1] can reorder a newer load (or store) before an older store on the same memory location, or it would break even single threaded programs.
The check done by Intel has false positives and it is possible that other cpus have stronger aliasing resolutions (or avoid the reordering completely, although it is unlikely for an high performance cpu), but it is not because of the x86 MM.
[1] Well, I guess some exposed pipeline VLIW might kind of do it, but that's another story.
Your parent post didn't imply that one can reorder loads/stores in a way that breaks the abstract machine on a single core. Load/store ordering is generally a multi-core concern.
The x86 memory model is widely known to be stricter than that chosen by default for most other CPUs. It's for that reason that Apple's X1 had to introduce total store ordering for x86 emulation at speed.
I read the parent as a comment on the article that discusses the machinery that allows reordering of potentially aliasing operations.
If that's not the case, I'm not sure how their comment is relevant.
I'll also just note that Intel actually slightly strengthened the documented MM in recent year from Processor Ordering to Total Store Order which formally forbids IRIW that never happened in practice.
Not more than almost, I hope. Intel did this to themselves, they could have easily deprecated things and then drop them after 15 years or so. They consciously chose to keep dragging along 35 years old cruft.
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[ 4.6 ms ] story [ 28.7 ms ] threadThey tried to get rid of strictly ordering almost all load/stores with Itanium, but they bungled that product so hard. Now switching ISAs would look like a weakness no matter what they do.
The check done by Intel has false positives and it is possible that other cpus have stronger aliasing resolutions (or avoid the reordering completely, although it is unlikely for an high performance cpu), but it is not because of the x86 MM.
[1] Well, I guess some exposed pipeline VLIW might kind of do it, but that's another story.
The x86 memory model is widely known to be stricter than that chosen by default for most other CPUs. It's for that reason that Apple's X1 had to introduce total store ordering for x86 emulation at speed.
If that's not the case, I'm not sure how their comment is relevant.
I'll also just note that Intel actually slightly strengthened the documented MM in recent year from Processor Ordering to Total Store Order which formally forbids IRIW that never happened in practice.