Warp-V: A RISC-V CPU Core Generator Supporting MIPS ISA

Hard to extract any useful information from that blog post. Was it written by a bot?

EDIT: I am the article writer’s father.

Interesting. Anyone knows what's the benefit of TL-Verilog compared to a next gen HDL like nmigen?

Robert Baruch used it extensively for his own RISC-V CPU implementation. Its channel is well worth watching for those interested in CPU design.

mhh__ 4y ago ↗

They have a good summary of the language and why it is what it is on their website.

What makes nmigen next gen? Is it even strictly a HDL?

Warp-V: A RISC-V CPU Core Generator Supporting MIPS ISA (cnx-software.com)