What am I missing? What is the 'small' / 'big' core distinction ? No avx512 (but still vnni?) ? Low number of floating point units? No vectorized fp, but all-in on integer units?
Is it a pentium m/core save out of the pentium 4 moment? Is there a plan to put more of those small cores together? I mean I'd be pretty interested in a 256 core machine with 'only' skylake per-core performance...
it small in size，around 1/4 the size of big "Golden Cove" core. Gracemont is a big architecture enhancement over Tremont Core, which is nurtured by the legendary Jim Keller.
No avx512, but not skimpy in floating point.
The rumor is that Intel "Sierra Forest" will contain huge amount of small cores.
Ah thanks. Although even without so many cores, I got ideas on how to saturate all those new ports. Am I reading that those cores have an awful lot of execution ports?
I hope Intel settles down soon to actual product lines I'm having a very hard time predicting anything right now... As are most of the oems we buy from...
Huge improvement to IPC and Energy efficiency. It is possibly the perfect CPU core for 90% of x86 computing usage. To me it was the most important announcement from Intel Architecture Day. So I was surprised and sad how little attention it was given and media doesn't seems care much.
Assuming those numbers were done with 4MB L2 Cache and not the 2MB version. And Depending on which Skylake Core variant they were comparing against, a Quad Core Gracemont is anywhere from 8mm2 to 13mm2. For comparison an ARM Quad Core N1 on TSMC 7nm is about 5.6mm2. Both inclusive of L2 Cache.
I actually want to see a 64 or even a 128 Core version to be used on Server. Or a cheap $10 x86 SoC for NAS and other applications.
A 64/128 core variant would effectively be a revival of their Xeon Phi line, which, in its later days, was basically this. It seems inevitable we'll see it again. My guess is it'll happen after Intel gets comfortable enough with chiplets to ship decently binned parts at a reasonable price (probably by sharing chiplets with laptop chips or some other high-volume product)
I think mass market tech media doesn't know how to interpret the impact of efficiency cores or big/little designs for average PC users since the best effort example they've seen so far was Apple's M1, which changed other things at the same time. Meanwhile, enthusiast tech media doesn't care because their existing reference frame is almost exclusively performance cores. I think they'll be more inclined to see the first generation or two as a gimmick, and then a laptop-only thing if Intel catches up on the performance core side.
The dream I always had with big.little designs was the ability to reduce context-switch related load.
It seems like right now, we're interrupting the cores every few tens to hundreds of milliseconds. Even if the scheduler says "Okay, nothing else worth running, resume what you're doing", you've still burned precious cache and branch predictor space.
If we knew that most of the "interactive" stuff that had to be snappy-- the OS, your UI threads, and any other tasks, were tossed on other "little" cores, you could reserve a "big" core with more "cooperative multitasking" semantics-- you'd only have to only yield to the scheduler when you're ready. Maybe add a (comparatively) very long watchdog to (maybe 30 seconds or a few minutes) to protect against someone reserving a core and promptly crashing. Then you can have a light-weight "pet the watchdog" operation instead of a full context switch run through the scheduler.
10 comments
[ 1.6 ms ] story [ 32.9 ms ] threadIs it a pentium m/core save out of the pentium 4 moment? Is there a plan to put more of those small cores together? I mean I'd be pretty interested in a 256 core machine with 'only' skylake per-core performance...
The rumor is that Intel "Sierra Forest" will contain huge amount of small cores.
I hope Intel settles down soon to actual product lines I'm having a very hard time predicting anything right now... As are most of the oems we buy from...
Assuming those numbers were done with 4MB L2 Cache and not the 2MB version. And Depending on which Skylake Core variant they were comparing against, a Quad Core Gracemont is anywhere from 8mm2 to 13mm2. For comparison an ARM Quad Core N1 on TSMC 7nm is about 5.6mm2. Both inclusive of L2 Cache.
I actually want to see a 64 or even a 128 Core version to be used on Server. Or a cheap $10 x86 SoC for NAS and other applications.
Yeah, it just such a great idea with great execution, but most people just don't realize it yet. It like the chiplet situation with Zen.
I think mass market tech media doesn't know how to interpret the impact of efficiency cores or big/little designs for average PC users since the best effort example they've seen so far was Apple's M1, which changed other things at the same time. Meanwhile, enthusiast tech media doesn't care because their existing reference frame is almost exclusively performance cores. I think they'll be more inclined to see the first generation or two as a gimmick, and then a laptop-only thing if Intel catches up on the performance core side.
It seems like right now, we're interrupting the cores every few tens to hundreds of milliseconds. Even if the scheduler says "Okay, nothing else worth running, resume what you're doing", you've still burned precious cache and branch predictor space.
If we knew that most of the "interactive" stuff that had to be snappy-- the OS, your UI threads, and any other tasks, were tossed on other "little" cores, you could reserve a "big" core with more "cooperative multitasking" semantics-- you'd only have to only yield to the scheduler when you're ready. Maybe add a (comparatively) very long watchdog to (maybe 30 seconds or a few minutes) to protect against someone reserving a core and promptly crashing. Then you can have a light-weight "pet the watchdog" operation instead of a full context switch run through the scheduler.