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Price must also be absurd.
Absurd that an article about RAM speed doesn't show a single number/figure about said RAM speed.
It does mention it is DDR5-7200. So 7200 MT/s in burst mode. Of course the other timing numbers are arguably also pretty critical, and we don't have any information about that.
It will probably be only a few percent improvement in individual cell access time. Pretty much all RAM performance improvements have been in expanding parallelization which only improves burst access.

They should think about scatter/gather style commands to start breaking this wall. Not everything benefits from pure sequential access.

No real argument about that. I certainly feel it is a bit misleading that the main number only applies to sequential access bursts, and that there is a fairly short burst length limit too, making sustained throughput at the quoted rate infeasible, even for sequential access. And actual random access frequently requires row changes which slows the effective rate even more.

I'm not sure if more complex command sequences like scatter gather is really the solution but is certainly seems worth investigating.

Usually the burst time is proportional to the bus transfer rate divided by the cell access time. It's designed to maximize random access while ensuring you can fully utilize the bandwidth on the memory bus. So you can keep issuing sequential reads and to a rough approximation achieve near 100% bus utilization. Depending on memory timings this may or may not always fully work out.

You can achieve some approximation of scatter/gather at the bank level as each bank is fully independent. But usually these are too far away in terms of address space to be utilized effectively. Scatter/Gather would help e.g. accessing an array at offsets larger than the burst size.

Cool. And we will still pay waaaay too much $ to upgrade to 32GB in the most high-end Apple-Silicon laptop coming this year (hopefully)