Agiler: An adaptive heterogeneous tile-based many-core arch for RISC-V (ieeexplore.ieee.org)

Wonder what sort of computational tasks this architecture is particularly suitable for.

I appreciate the code snippets they put in the pub; when HW papers abstract that out, the system doesn't feel grounded in reality. Still, the open problem for this class of architecture IMO is programmability. A composable, well designed API for many core machines would be worth it's weight in gold.

Looking at the title and skimming the diagrams, vaguely reminds me of a souped-up TIS-100.

Transputer lives! Would be a lot of fun to tinker with one of these.