Are we ever going to circle back to the notion of creating circuits that can hold more than 2 states? We seem to be doing that for SSDs but not for logic.
Or has the space already been explored and there's nothing there?
What I was trying to say is that there are things we don't do because they're hard or we don't know how, and there are things that we don't do because we've proven they don't work.
Memristor and analogue processors to accelerate ML are doing this. Neural networks are ok with operations on noisy, analogue states. Analogue operations such as op-amp multiplication are more power hungry than individual digital gates, but some are less power hungry than digital multipliers which use thousands of gates.
For digital, noise-free logic, it's generally more power efficient and physically simpler to have logic gates operate on two cleanly separated states with more gates, than to have bulkier, more complicated gates that do the same thing with combined states. A transistor which is fully on or fully off in a logic circuit uses low power either way (like a wire or a gap in the circuit), but the in-between state uses more power (like a resistor, it produces heat). This is one reason why power consumption goes up with the amount of logic state switching (the in-between resistor-like state occurs briefly during each state change), and also why many-level stable logic states aren't so efficient, except with complicated gates that use many transistors to implement many thresholds.
For non-volatile storage, that doesn't apply. Information density is more important, individual memory cells do not change state often so switching power is less of a thing per memory cell, and the logic sits at the edge of the memory array, shared among many cells. The edge circuitry can afford to be more complicated, to optimise the bulk of the memory array.
In magnetic storage and communication, the signal processing to encode many states in a small signal takes considerable power, but the trade off is worth it.
> Memristor and analogue processors to accelerate ML are doing this. Neural networks are ok with operations on noisy, analogue states. Analogue operations such as op-amp multiplication are more power hungry than individual digital gates, but some are less power hungry than digital multipliers which use thousands of gates.
In-memory computing is just barely in active research. Unlike quantistors, memristors are being built (and have already been built) in many research laboratories.
If you are interested in learning, the idea of memristors (and other computational memory technology) is not to replace traditional memory, but rather to augment small portions of it with increased/additional computational functionality.
For example, you could add a (relatively speaking) extremely small number of memristors to an existing memory module, load two matrices into that area of memory, and reading from the adjacent region of memory would immediately yield the result of multiplying those two matrices. If you could simply instruct the RAM module where the existing data lies, this would be an immense boost in efficiency to AI/deep learning prediction algorithms. Here is a video explanation of how this could be use to perform matrix vector multiplication in O(1): https://youtu.be/30K5i8bdiyg?t=1492 .
That video mentions later that something similar can be used in solving linear and partial differential equations. Applications for deep learning training is discussed at 40:20 .
You'll notice everything discussed in the keynote has experimental results. At 41:27, he mentions that you can actually send images to their memristor chip over their website . Though the link is unfortunately dead, it definitely worked, and was in fact performing neural network computations using memristors over the network.
Analog circuits exist and are widely used in some applications including for stuff like inference in AI models. The issue is that they are somewhat inexact which is a huge problem for most conventional code. As for circuits which work in a discrete rather than continuous space, it's basically always better to just use binary to represent information because 2 states are the most easily separable. Once you have to start separating out more states things get more difficult and it's almost never worth the effort unless you're trying to do stuff like storage in SSDs.
Roughly speaking, an N-level digital logic system requires O(N) transistors in order to buffer/force a signal into one of N states, but only performs O(log(N)) more work with them relative to binary.
Without the buffering step, you'll eventually get the middle logic levels drifting (e.g. your "1"s become "0"s or "2"s). Binary gets this for "free" because there's no middle states; this doesn't apply just to a simple buffer, similar details apply to the implementation of all other gates (many of which are rather awkward to implement).
Analog works out for rough calculations because you can skip the buffering process, at the expense of having your calculation's precision limited by the linearity of your circuit.
SSDs are more of a special case, because to my knowledge they're not really doing work on multi-level logic outside of the storage cells. They pump current in on one axis of a matrix, read it out on the other, and then ADC it back to binary as fast as possible before doing any other logic.
Random sidebar: I don't see any constraint like this for mechanical computers, so a base-10 mechanical computer doesn't strike me as any more unreasonable than a base-2 mechanical computer (i.e. slop and tolerance is independent of gear size). In fact, it might be reasonable to say you should use the largest gears that the technology of your time can support (sorry Babbage).
From the last one, ca. 1988 ASML was failing badly:
"But in a market of fierce competition and many suppliers, the small unknown company from the Netherlands couldn’t catch a break. ASML had few customers and was unable to stand on its own two feet. Making matters worse, shareholder ASMI was unable to maintain the high levels of investment with little return and decided to withdraw, while the global electronics industry took a turn for the worse, and Philips announced a vast cost-cutting program. The life of our young cash-devouring lithography company hung in the balance. Guided by a strong belief in the ongoing R&D and in desperate need of funds, ASML executives reached out to Philips board member Henk Bodt, who persuaded his colleagues to lend a final helping hand."
(I understand that nowadays you need their equipment for new fabs.)
Interesting how the present came from a very fragile, almost non happening past.
A lot less critical, I've read that Olivetti vanished from the industry due to random finance wars between France and Belgium with some bank (which bought the company not long before) crashing and thus cutting money right at the moment where PC were taking off.
Crazy to think about where we'd be without ASML right now. Would another company have stepped up to fill the void? Or was there something unique about ASML that allowed them to reach EUV instead of anybody else?
Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer.
So how are the multiple layers done, if light is shined on the surface, how do you reach the other layers? And how is this doping done, you also need to choose what element goes where but this couldn't be done with light and a mask I'd think (so even if single layer I wonder how this works)? And how do you reach the other layers with those chemical elements for doping?
It’s built from the bottom up in layers (at least traditionally, I’m not sure how the newer 3D structures for memory are constructed). The bottom layer of silicon substrate is covered in an oxide and etched selectively by photoresist and masking. Further layers are connective layers of metal lines insulated by oxide, with vias connecting metal layers to one another. The same oxide deposition, photoresist, expose, etch process is used for each layer.
You can only ever reach exposed surfaces. This means a very complex sequence of adding and removing layers to expose/hide things so that the currently exposed surface features are what you want to change in the current processing step.
That’s because they skip quite a few steps. You would first deposit a photosensitive layer, then expose it wit a pattern of light, which will allow you to selectively open up the parts you want to toch next.
For step 7 for example, you create a masking layer that way, after which you etch away only the exposed parts where source and drain contacts will end up.
For step 8, you do something similar. The openings you’ve etched in step 8 will allow only to dope the contacts, but you need to mask the nmos and pmos separately, otherwise you get the same doping in both transistors.
A lot of the ‘magic’ to make this work is in the materials and chemistry: you need selectivity: etching that only interacts with the exposed parts. In highly scaled finfet nodes, the material combinations are very complex as you sometimes want 2, or 3 different material combinations to interact in the way you want, reliably, at nanometer scale.
Each wafer has only one layer of transistors. They then have many layers of wiring on top. They go through semiconductor manufacturing with one layer of transistors.
For each layer of metal, they go through several steps of deposition of insulator, masking, etching, deposition of metal (often in several passes now), grinding or etching that, and then covering it all up with more insulator and grinding that layer down to produce a smooth surface for the next layer.
Once the chips are complete, 3D stacking is a packaging process. It involves grinding the backsides of the chips down until they are very thin and attaching the dies together using vias that run through the thin remaining silicon layer.
EDIT: Flash memory today has multiple stacked doped silicon layers, but it is a special process that is largely unsuitable for logic.
There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D integration, which we have had for a decade, is at the tipping point as we move to new nodes and start making monolithic integration a thing. Ultra low power energy efficient compute at the edge, we're talking consuming less power in a year than it takes me to think about what I want to say when writing this comment right now. On-die microfluidic cooling for 3D dies is starting to appear. On-die sensors for new camera tech. We're edging up to a point where multiple sensors and/or a camera, compute, model inference and mesh network connectivity all exist on a single die.
Together with memristors, in-memory compute is likely going to be a big deal. It's already here in some forms, see e.g. Content Addressable Memory in high end networking gear.
They're definitely not huge right now and I haven't seen any viable paths toward them becoming a big thing any time in the near future. There's barely any work being put into them relative to other stuff in the field. HP made some big claims years back but have totally failed to deliver anything and I haven't heard anything about the technology in years.
Prior to the pandemic I had the privilege, due to my wife's position, of attending five or so IEEE conferences per year in the subject of microelectronics and got to see a lot the small enhancements. 15 years ago MEMS and SOI was all the rage, and it moved at glacial pace, and "nothing was coming of it." Now you cannot pick up a modern smartphone without having most of those small developments packed inside it. It's frustrating in one way, seeing the cute piglet of a fringe idea entering the pipe, and wondering if it will come to aught, and astounding to finally put the metaphorical sausage of productization in your mouth many years later thinking to yourself "Oh, I had forgotten all about that..." I use the food metaphor because my wife used to work in market research (prior to her career in running 30,000+ attendee conventions and highly technical microelectronics conferences for the IEEE) and those tasty MSG-laden noodles we all devoured on a student's grocery budget took years of refinement through market testing before they became a real product available universally everywhere.
More than 20 years ago, I read about new FRAM/FeRAM chip that just got commercialized that was supposed to revolutionize non-volatile storage. And the specs were pretty good, definitely much better that flash.
And yet today, nothing came out of it. Sure, you can still buy FeRAM at digikey, and it found a niche or two by itself, but it is tiny, tiny piece of overall storage market.
I think that memristor is going to end up as FRAM and not as MEMS. It is cute, but even if it could be executed perfectly, it does not allow anything that more conventional technologies can do (unlike MEMS :) l
I remember FRAM now that you mention it. There's obviously a lot of promising technologies that die through poor marketing, poor adoption, price, better performing or cheaper alternatives. I see potential in memristors but I think the jury is still out on whether it will see marketplace success. I personally think it has huge upside potential but it sounds like both of us have seen all that be for nothing. I think my previous comment carries more weight though, because it has a pig on it.
I feel like memresistors have been hyped since HP tried to use it to save their business from 2007-2015. Nothing ever came from it from HP at least. Have there been new developments that make it more likely to be viable?
A lot of technology that's out at the fringes will often be hyped up by a marketing department. It is the culinary equivalent of telling everyone how awesome the soup is going to taste just as the cook is returning from the grocery store with the unprepared, raw ingredients. We're edging closer to the "needs seasoning." There's always some company trying to sell something that doesn't really exist in a production form, and then 10 years or 20 years later, it is so in the background we don't even think of it anymore. You know how pricing works? Multiply by ten for every step from cost of raw materials to a commercial product in your hand? 10x to turn the raw materials in components. 10x to turn components in to a product. 10x to move the product to the store. 10x to sell it to you as an item you can use. Same kind of idea when it comes to technology research, but in terms of time. Six months of research becomes five years of development becomes ten years of commercialization becomes twenty years of "it's everywhere."
I'll point out that transistors were invented in 1947 and the computer industry made the switch from vacuum tubes to transistors around 1958. Integrated circuits were invented in 1958 and the computer industry switched to them around 1965. My point is that historically the computer industry has been able to switch to a completely new technology a decade after it's invented. HP's memristors have been around for 15 years and haven't made much impact.
If you look at IBM's history you can see how reliability and the ability to manufacture components in quantity played a huge role in the adaptation of both. Bell Lab's early point contact ones weren't manufacturable. IBM didn't move to proper ICs until 1970 with the System/370 because anything they made including the low end would be sold in quantities too high for ICs before then (System/360 Models 85 and 195 preceded the 370s by 1-2 years, but they only sold 60 total units).
No idea. For example, between the development of core memory and DRAM there were a host of technologies they tried because core is slow and expensive to manufacture. The best they did for speed was called thin-film, and they sold only two systems with it, upgrades of the System 360 Model 91 supercomputer named the Model 95. They had 1 MiB of it and 4 MiB of core, sold to NASA, the first Model 91 customer: https://en.wikipedia.org/wiki/IBM_System/360_Model_91
MEMS means Micro-Electro-Mechanical Systems, iow. a category of a type of sensor/actor elements that work with mechanical effects but are minuscule and often constructed using lithographic processes, not milled or the like.
Comments felt like they conflated them. Also what are all the MEMS chips in phones? Another element of the threads is they're all over phone builds. The accelerometer? The lens systems?
We always have this discussion in these threads. There should be a HN wiki for these things. It's not just a name because it does measure true progress over time. We should just use density of transistors per area because that is increasing at the same rate as the name of the process is decreasing. It's just been done in other ways than just shrinking every feature. This article is about one of those steps in the design of the transistor that allows for that density increase. That 3 nanometers is not a feature size doesn't mean that it's "just marketing" either like it's often claimed. The process node scale does measure true progress. It's just unfortunate that we ended up with feature size instead of density for that scale because of historic reasons.
Just because it has meaning doesn't mean it's not just a name unrelated to the feature size it appears to refer to. I never said it's "just marketing", it does have meaning, but that meaning is not a length. It measures progress, but no longer measures feature size.
Whatever the future holds, it’s clear that the industry is in no hurry to abandon silicon, despite the theoretical advantages of alternative materials.
“””
Such as? What a frustrating way to leave us dangling.
But they are harder and/or more expensive. That being said, they certainly don't have anywhere close to the amount of investment and research so there's probably some room to close the gap.
Gallium Arsenide. Semiconductor with certain nicer properties than silicon that allow it to switch faster and have a larger operating temperature at the cost being harder and more expensive to manufacture. That's a fairly big caveat, being a lot of the reason why silicon is so ubiquitous, relegating adoption of other semiconductors to more niche applications where their more optimal properties are a necessity.
58 comments
[ 3.1 ms ] story [ 71.3 ms ] threadOr has the space already been explored and there's nothing there?
What I was trying to say is that there are things we don't do because they're hard or we don't know how, and there are things that we don't do because we've proven they don't work.
Ternary does have some cool features though.
For digital, noise-free logic, it's generally more power efficient and physically simpler to have logic gates operate on two cleanly separated states with more gates, than to have bulkier, more complicated gates that do the same thing with combined states. A transistor which is fully on or fully off in a logic circuit uses low power either way (like a wire or a gap in the circuit), but the in-between state uses more power (like a resistor, it produces heat). This is one reason why power consumption goes up with the amount of logic state switching (the in-between resistor-like state occurs briefly during each state change), and also why many-level stable logic states aren't so efficient, except with complicated gates that use many transistors to implement many thresholds.
For non-volatile storage, that doesn't apply. Information density is more important, individual memory cells do not change state often so switching power is less of a thing per memory cell, and the logic sits at the edge of the memory array, shared among many cells. The edge circuitry can afford to be more complicated, to optimise the bulk of the memory array.
In magnetic storage and communication, the signal processing to encode many states in a small signal takes considerable power, but the trade off is worth it.
I checked Mouser just now and memristors are not in stock: https://www.mouser.com/c/?q=memristor
If we are talking about imaginary components, then I think quantistors will change everything.
If you are interested in learning, the idea of memristors (and other computational memory technology) is not to replace traditional memory, but rather to augment small portions of it with increased/additional computational functionality.
For example, you could add a (relatively speaking) extremely small number of memristors to an existing memory module, load two matrices into that area of memory, and reading from the adjacent region of memory would immediately yield the result of multiplying those two matrices. If you could simply instruct the RAM module where the existing data lies, this would be an immense boost in efficiency to AI/deep learning prediction algorithms. Here is a video explanation of how this could be use to perform matrix vector multiplication in O(1): https://youtu.be/30K5i8bdiyg?t=1492 .
That video mentions later that something similar can be used in solving linear and partial differential equations. Applications for deep learning training is discussed at 40:20 .
You'll notice everything discussed in the keynote has experimental results. At 41:27, he mentions that you can actually send images to their memristor chip over their website . Though the link is unfortunately dead, it definitely worked, and was in fact performing neural network computations using memristors over the network.
https://twitter.com/kenshirriff/status/1046436838146113536
Without the buffering step, you'll eventually get the middle logic levels drifting (e.g. your "1"s become "0"s or "2"s). Binary gets this for "free" because there's no middle states; this doesn't apply just to a simple buffer, similar details apply to the implementation of all other gates (many of which are rather awkward to implement).
Analog works out for rough calculations because you can skip the buffering process, at the expense of having your calculation's precision limited by the linearity of your circuit.
SSDs are more of a special case, because to my knowledge they're not really doing work on multi-level logic outside of the storage cells. They pump current in on one axis of a matrix, read it out on the other, and then ADC it back to binary as fast as possible before doing any other logic.
Random sidebar: I don't see any constraint like this for mechanical computers, so a base-10 mechanical computer doesn't strike me as any more unreasonable than a base-2 mechanical computer (i.e. slop and tolerance is independent of gear size). In fact, it might be reasonable to say you should use the largest gears that the technology of your time can support (sorry Babbage).
https://semiengineering.com/entities/asml/
https://en.wikipedia.org/wiki/ASM_International
https://www.asml.com/en/company/about-asml/history
From the last one, ca. 1988 ASML was failing badly:
"But in a market of fierce competition and many suppliers, the small unknown company from the Netherlands couldn’t catch a break. ASML had few customers and was unable to stand on its own two feet. Making matters worse, shareholder ASMI was unable to maintain the high levels of investment with little return and decided to withdraw, while the global electronics industry took a turn for the worse, and Philips announced a vast cost-cutting program. The life of our young cash-devouring lithography company hung in the balance. Guided by a strong belief in the ongoing R&D and in desperate need of funds, ASML executives reached out to Philips board member Henk Bodt, who persuaded his colleagues to lend a final helping hand."
(I understand that nowadays you need their equipment for new fabs.)
A lot less critical, I've read that Olivetti vanished from the industry due to random finance wars between France and Belgium with some bank (which bought the company not long before) crashing and thus cutting money right at the moment where PC were taking off.
So how are the multiple layers done, if light is shined on the surface, how do you reach the other layers? And how is this doping done, you also need to choose what element goes where but this couldn't be done with light and a mask I'd think (so even if single layer I wonder how this works)? And how do you reach the other layers with those chemical elements for doping?
And I believe there were steps to flatten and I believe effectively sand the surface flat after some layers.
Would note that since FinFETs, deposition occurs from the side as well as top.
The Wikipedia article on CMOS has a very nice illustration of the basic steps of this process: https://en.wikipedia.org/wiki/CMOS#/media/File:CMOS_fabricat... Current processes are much more complex than even that.
For step 7 for example, you create a masking layer that way, after which you etch away only the exposed parts where source and drain contacts will end up.
For step 8, you do something similar. The openings you’ve etched in step 8 will allow only to dope the contacts, but you need to mask the nmos and pmos separately, otherwise you get the same doping in both transistors.
A lot of the ‘magic’ to make this work is in the materials and chemistry: you need selectivity: etching that only interacts with the exposed parts. In highly scaled finfet nodes, the material combinations are very complex as you sometimes want 2, or 3 different material combinations to interact in the way you want, reliably, at nanometer scale.
(Edit finfet not finger)
For each layer of metal, they go through several steps of deposition of insulator, masking, etching, deposition of metal (often in several passes now), grinding or etching that, and then covering it all up with more insulator and grinding that layer down to produce a smooth surface for the next layer.
Once the chips are complete, 3D stacking is a packaging process. It involves grinding the backsides of the chips down until they are very thin and attaching the dies together using vias that run through the thin remaining silicon layer.
EDIT: Flash memory today has multiple stacked doped silicon layers, but it is a special process that is largely unsuitable for logic.
And yet today, nothing came out of it. Sure, you can still buy FeRAM at digikey, and it found a niche or two by itself, but it is tiny, tiny piece of overall storage market.
I think that memristor is going to end up as FRAM and not as MEMS. It is cute, but even if it could be executed perfectly, it does not allow anything that more conventional technologies can do (unlike MEMS :) l
Memristors are a specific electric component.
https://en.wikipedia.org/wiki/Microelectromechanical_systems
https://en.wikipedia.org/wiki/Memristor
While MEMS is already huge and still getting way bigger, memristors ain't really a thing yet.
Impressive.
Whatever the future holds, it’s clear that the industry is in no hurry to abandon silicon, despite the theoretical advantages of alternative materials. “””
Such as? What a frustrating way to leave us dangling.