Self-Modifying FPGAs?
In order to do this form of "finger learning" I start with a state machine encoding the initial actions. A JIT-like mechanism recognizes repeated actions, collects up the sequence, optimizes the total sequence, and then creates a new additional state, thus "getting things into the fingers".
Ideally I'd like an FPGA that could dynamically self-modify. It would be able to change lookup tables (LUTS) and pathways within itself, thus changing the recognized state logic.
The only path I know about would be to change the RAM that holds the initial state and then reboot.
That path requires deep knowledge of the binary blob that gets loaded when creating the FPGA design.
Changing that binary blob, as far as I know, involves going back to a Verilog compile and then through tools to do place-and-route, etc. This tedious path is my current effort.
So the question is: Is there an FPGA capable of directly self-modifying by writing LUTS or by writing RAM?
Ideally this self-modifying FPGA would have an embedded hard processor (RISC-V) that could read/write LUTS and pathways in the rest of the FPGA. The hard processor would run self-aware tasks like the JIT.
I know Intel has a CPU/FPGA combination (only available to data center scale vendors unfortunately) that MIGHT be able to self-optimize repeated instruction paths. This might be difficult on an X86 architecture but it might be reasonable on a RISC-V architecture which allows non-standard instructions.
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[ 3.6 ms ] story [ 33.3 ms ] threadThat capability is called "partial reconfiguration" and is pretty common. Your description sounds like you would like to reconfigure the FPGA at a finer grain level than what "partial reconfig" does. Also, FPGA internals (WRT configuration) are typically undocumented and often proprietary, so having the FPGA self-generate FPGA configurations is going to be difficult unless the FPGA in question is well documented.
Using the FPGA to reconfigure itself might be tricky since FPGAs are typically loaded by an external source. Theoretically, you could generate the new configuration, write it to an external memory (e.g. RAM), and then use the FPGA load-from-memory capability to do what you ask. There is a wide gap between theory and practice here, however.
By the time you implement configuration generation and reloading in an FPGA, you probably will be out of room in the FPGA. :-/
https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
You can add Morphle Logic to any processor including RISC-V and program/reconfigure the gate array by just writing SRAM. So you can reprogram small parts in nanoseconds if you want, even while the circuit is running! We've added a small RISC-V processor to make it easy to reprogram the Morphle Logic.
There is a small caveat: you can not buy our chips yet... I need $100K and 3 months to tape out new chips first.
An equivalent Morphle Logic of a small FPGA like the ICE40 would cost half a dollar, the equivalent of an Virtex Ultrascale would cost around $600. Some parts of these reconfigurable arrays could run at 12 Ghz.
Email us at morphle [at] ziggo { dot} nl
The second is a $5 10 core processor with 6 Megabyte memory for IoT, gigabit ethernet and Morphle Logic to compress video streams Squeak Smalltalk over ethernet. Much faster than a Raspberry PI 4 with a 4K camera, but not $100 but just $5 total cost.
> though more as a spectator than a participant in recent years,
That is a pity, I was hoping you would be a grad student or similar that could do a Masters or PhD thesis writing our software for the asynchronous manycore processor and the ‘asynchronous’ gate array. Maybe you can help me locate another student who would do his masters with us? Any volunteer would be helpful, it's just that we don't pay any salaries. But we do hand out samples......
I had a lecture on a larger version of this, a million core wafer scale integration running Smalltalk: https://vimeo.com/731037615