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Ask HN: If the CPU redesigned today, with no legacy incentives what can change?

5 points by LangIsAllWeNeed ↗ HN
Something I often hear is that the modern CPU has bunch of sort of “poly fills” to merge the programming paradigms of past with new tech. Microcode perhaps mostly. Like that C programming, which mostly forms basis for other absractions no longer captures how a cpu works, and the cpu tries to optimize C type abstractions for modern post 80/90s innovations.

What would a new paradigm for CPU and GPUs look like? Is there some aspect of the legacy system that is not ideal but clearly economically impossible to change. Does the poly fill type design of cpu microcode have drawbacks?

One analogy is planes. Plane design has remained pretty unchanged since 1960s because of regulations, very different design = pay to retrain pilots. Of course planes have still drastically improved across board, but but they are still controrting themselves to adhere to the paradigm of the pilots for economic reasons. Without this, a new plane design might be quite different. (This is part of the Boeing crisis- the software was designed to “polyfill” the change in flight beahvior caused by the contorting themselves to get a better engine on similiar plane frame)

21 comments

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warrenm
Planes have remained pretty much unchanged because aerodynamics works the same for everyone

Unless you mean cockpit design :)

eimrine
I refuse to understand your C programming point, but answering your question, a computer might be a Lisp machine and/or having von-Neumann architecture instead of Harvard one. CPU might be more multithread and GPU might be better suited for such things as calling eval().
t-3
> having von-Neumann architecture instead of Harvard one.

I think you got that backwards. Von Neumann is mainstream and a few MCUs use Harvard architecture.

eimrine
So why a CPU cache (L1 L2 L3) has 2 halves, one for code and another for data?
t-3
Can you directly choose what goes into the cache or is it just a technical optimization? Which instructions read and write the cache?
zerohp
You can directly choose what is available on the instruction side by using the XN (aka XD) permission bits in the page table. Other mechanisms exist to make pages readable by instruction fetch but not readable by the data side.

Von Neumann vs Harvard is a pointless discussion. Both are too simplistic describe modern architectures.

LangIsAllWeNeed
How would you understand the c to architecture connection?

I have read that C ideas are baked into how higher level programming languages work, but modern cpus are a lot more parallel and some other things than most languages fail to account for, so the microcode tries to bridge gap.

Leftium
1. [Ternary computers]: Base-3 is the most efficient of all integer bases; numbers are stored most economically with trits.

2. Something like a [Lisp machine] that is optimized for functional-style programming with immutable data.

[Ternary computers]: https://www.wikiwand.com/en/Ternary_computer

[Lisp machine]: https://www.wikiwand.com/en/Lisp_machine

bruce343434
Heap trees would be less efficient with trits. What do you mean "most efficient of all integer bases"?
Leftium
Ternary minimizes both the length and number of different symbols used to express a range of numbers[1].

Heap trees were probably optimized for binary, since that's what we use. Perhaps there would be a ternary version of heap trees? Or a totally different ternary data structure that serves the same purpose?

[1]: https://math.stackexchange.com/questions/446664/what-is-the-...

Leftium
Slightly off topic, but I'm curious why some users start a comment with "* * *", then edit it later? Is this just a HN thing?

(Parent comment happened to start as one of these "* * *" comments.)

bruce343434
Do you mean my comment? I did not write nor remove "* * *".
Leftium
Oh, interesting! According to HN Replies, that was the content of your comment (https://imgur.com/t5316Rx) (When I checked on HN, it was not "* * *")

I've seen these ephemeral "* * *" comments before, and even another comment asking about them.

bruce343434
That is interesting, perhaps a synchronisation error? As if the actual comment wasn't available yet but the email already got sent.
Leftium
I don't think it's just an HN Replies email thing. I've seen "* * *" in actual HN comment threads, too.

And I've seen it in 100% of your replies to me, when I've never seen it for other replies. So I wonder if it's related to how you use HN

__ryan__
This is definitely solely an HN Replies thing.
Leftium
This is the first time I've seen it in my HN Replies, but I have seen "* * *" before on https://news.ycombinator.com/. I even saw another comment asking about this type of comment.
__ryan__
Do you have any HN-related extensions installed?

Edit: I truly did not believe you, but it appears to maybe be the “delay” feature [0]. Users with a delay set might show the asterisks until the delay passes.

My apologies.

0: https://news.ycombinator.com/item?id=231024

Am4TIfIsER0ppos
Without being too radical you might merge some things. Hardware detection like on x86. Feature identification like on x86 (cpuid). Fixed size instructions seem to be "more popular". Variable length vector operations/loops seem intriguing (decent presentation about it at fosdem this year).

What's probably going to happen is more integration and more drm.

bjourne
I think next gen cpus should be tuned for actual workloads rather than the synthetic benchmarks they are often designed to beat. Essentially latency and not throughput. Right now I'm entering text into a text field on a web page and I don't care about sustained throughput but it would annoy me greatly if, say, switching tabs would cause noticeable lag and/or make the noisy cpu fans spin up.

How do you optimize architectures for event-based "do nothing 99.9% of the time, do A LOT 0.1% of the time" workloads? I don't know. My hunch is that you should prioritize memory latency and pay more attention to worst case rather than best case performance.

rthomas6
I can almost guarantee, for this problem, the current processors could perform to your expectations, and any problem lies in the way the software is written (prioritizing developer time over performance).