What’s interesting to me is how big the steps in process node sizes are. I thought the 5nm to 3nm step was huge—it’s a 40% reduction! And 3nm to 2nm is similar—a 33% reduction. But then I looked at wikipedia’s list of process node sizes and, well, they’ve all been 30% to 50% over more than five decades. Which is of course Moore’s law, but I figured there would be more, smaller steps.
"The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers"
How much of moore's law has simply been foundries just choosing to make smaller steps to secure a nice roadmap of product offerings? Have any significant changes been made to EUVL that prevented them from making 2nm chips a decade ago? Or were the learnings along the way what got them here.
Are these chips actually what was being envisioned when folks were talking about sub 10nm back then in terms of the real feature sizes and performance?
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[ 2.7 ms ] story [ 49.9 ms ] threadWill US retake semico node leadership or TSMC will continue to be #1?
Who is even remotely nipping at TSMC's heels at their scale?
And what is Node Leadership? And how to you define Number 1? By Tech, by volume, by revenue or by profits?
https://en.wikipedia.org/wiki/List_of_semiconductor_scale_ex...
https://en.m.wikipedia.org/wiki/3_nm_process
It used to be defined by the size of gate iirc - that is why people say it has no relation to the physical features.
And now I wonder what kind of physics will be investigated for sub nanometer electronics .. spin ? neutronics ? photonics ?