i work in both of these areas (compilers [contrib on iree/mlir] and RTL); they're not even remotely doing the same thing. iree is a runtime environment (Intermediate Representation Execution Environment) - it's not even a compiler, most of the passes come from upstream - while calyx aims to be a lot of things but you could boil it down (for the purposes of keeping this response short and to the point) to HDL+core generator.
If you work on FPGA’s, are there any HLS systems that you think are good enough to implement most of the techniques we see in the AI research papers? Especially those reducing the cost of pre-training or increasing the context of models.
> are there any HLS systems that you think are good enough to implement most of the techniques we see in the AI research papers? Especially those reducing the cost of pre-training or increasing the context of models.
you're talking about two different worlds that are universes apart.
fact 1: no matter what anyone tells you (calyx included), you cannot splat NNs onto silicon (neither FPGA nor ASIC) - i spent probably thousands of hours trying to do it for CNNs and the results were completely unimpressive. why? because routing and statically scheduling is NP-hard. what people do (what i'm doing now) is build GEMM accelerators and then contort their NN layers into sequences of GEMMs.
fact 2: HLS will never work for anything larger than toy problems because scheduling is NP-hard (see 1).
> I used to look for tools that bypass most of the hardware design
so you can absolutely, without a doubt, give up on this dream (until knuth proves NP=P).
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[ 3.2 ms ] story [ 28.8 ms ] threadBias: I implemented an integration for iree.
https://www.synflow.com/
If you work on FPGA’s, are there any HLS systems that you think are good enough to implement most of the techniques we see in the AI research papers? Especially those reducing the cost of pre-training or increasing the context of models.
you're talking about two different worlds that are universes apart.
fact 1: no matter what anyone tells you (calyx included), you cannot splat NNs onto silicon (neither FPGA nor ASIC) - i spent probably thousands of hours trying to do it for CNNs and the results were completely unimpressive. why? because routing and statically scheduling is NP-hard. what people do (what i'm doing now) is build GEMM accelerators and then contort their NN layers into sequences of GEMMs.
fact 2: HLS will never work for anything larger than toy problems because scheduling is NP-hard (see 1).
> I used to look for tools that bypass most of the hardware design
so you can absolutely, without a doubt, give up on this dream (until knuth proves NP=P).