Ask HN: How to turn off x86 Pipelining
Product Owner wants to reduce work-in-progress (WIP). After a long conversation with a micro architecture guy, to make a long story short, I have a user story to turn off instruction pipelining on our production servers.
The story I have is only 1 story point so I need something that will not take more than a day to implement. So I need something that I can change to our software and nothing weird like changing BIOS settings or anything like that where I need to get IT involved.
13 comments
[ 2.7 ms ] story [ 54.8 ms ] threadThe reason I say there needs to be a very detailed research spike is because this is almost always the wrong solution to whatever the underlying problem is. A 1 point story with no implementation details means this came about from some pontificating around theory without any actual a/b testing.
Sorry I don't have the answer to this specific thing other than you say it seems your entire process is broken here and you need a architect or sr engineer to push back on this. At minimum to provide implementation details but ideally to actually have the research to support it.
There is a definitely a process problem going on in your organization if you are here asking this question. Either you should have gotten this answer from your "long conversation with a micro architecture guy" before pointing the story, or your PO should not have said this story is ready. Or both.
though, you haven't given enough context, so I could be totally off base. if you're working on a program and there's a particular part that you've been tasked to examine, you could put the appropriate x86 asm around that code to disable pipelining, which is an interesting idea, but that's still some heavy deep optimization work that would a lot more analysis than just "disable pipelining". they spent a lot of money to put it in CPUs for a reason.
If it were possible, it would be vastly more complicated than changing BIOS settings.
What is the specific problem they are trying to solve?
What parts of the actual implementation are contributing to that problem?
Which contributing parts are less important than solving the problem?
Or to put it another way, turning off x86 pipelining is probably an X creating an XY problem.
Good luck.
The closest you might be able to come is working to disable as much of the l1/l2/l3 caches, but I don't know if youncan do that in userland.
You might be able to do OS settings to run your cpu at a very low clock rate and pretend that's similar.
Even ancient chips like the 8088 and 6502 had some pipelining.