yosys [1] is the the open-source synthesis tool and also supports formal verification and other analysis.
however, it's Verilog front-end is basically Verilog-2005 with a hodge-podge of newer features added on but it is unfortunately very buggy and incomplete.
Mike Poploski's slang [2] is an absolutely top-notch System Verilog parser and elaborator that already supports nearly all System-Verilog 2023 features already.
why not adapt the slang front-end to yosys so we can have a proper modern System Verilog HDL entry with yosys's excellent synthesis and analysis engines?
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[ 4.1 ms ] story [ 19.2 ms ] threadhowever, it's Verilog front-end is basically Verilog-2005 with a hodge-podge of newer features added on but it is unfortunately very buggy and incomplete.
Mike Poploski's slang [2] is an absolutely top-notch System Verilog parser and elaborator that already supports nearly all System-Verilog 2023 features already.
why not adapt the slang front-end to yosys so we can have a proper modern System Verilog HDL entry with yosys's excellent synthesis and analysis engines?
Martin Povišer just did it! Thank you Martin.
[1] https://github.com/YosysHQ/yosys [2] https://github.com/MikePopoloski/slang