I really feel that hardware description languages could need some fresh air (especially the tooling), but on the other hand it must be insanely difficult to come up with s.th. that can compete with the major players.
A point of frustration for newer languages, that sus continues, is the lack of thought towards simulation and testbench design, and how it integrates with the language.
While it would be nice to have more elegant support for "modern" codegen in the sv/verilog/vhdl, the real unergonomic experiences are test bench design and integration. The only real options are (for sv, verilog, I have less experience with vhdl): use verilator and write your tb in cpp, use verilator and then write your testbench in cocotb, or you work at a chip design company and use one of the big 3's compilers and maybe you use UVM or cocotb. Verilator and cocotb are okay, but you're crossing a language boundar(ies) and referencing generated code -- it is both mechanical and complex to get any design working with it.
If sus had first class interfaces to create testbenches that could map to UVM or verilator, it would be much more interesting. Spade does some interesting things by having its own package manager, but doesn't (afaik) expose a ton within the language itself
as a HW designer that writes RTL for living I will repeat this 150 times and will put this on my gravestone: WE DONT NEED ANOTHER SHMANCY HDL. really. existing ones are moooooorrreeee than fine.
our tools suck, verification sucks. your design complexity is entirely limited by your verification capabilities (and automation infra). having fancy constructs for CDC or pipelining in HDL is utterly useless, especially that CDC checking is done by special tools that do it nearly perfect with a bit of constraints.
Hi everyone! Question for Verilog/VHDL Profis: What are your favorite documenting tools? Is there a way to automatically generate API for a project? I am looking for something like autodoc from sphinx but for Verilog.
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[ 37.3 ms ] story [ 628 ms ] thread> The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
While it would be nice to have more elegant support for "modern" codegen in the sv/verilog/vhdl, the real unergonomic experiences are test bench design and integration. The only real options are (for sv, verilog, I have less experience with vhdl): use verilator and write your tb in cpp, use verilator and then write your testbench in cocotb, or you work at a chip design company and use one of the big 3's compilers and maybe you use UVM or cocotb. Verilator and cocotb are okay, but you're crossing a language boundar(ies) and referencing generated code -- it is both mechanical and complex to get any design working with it.
If sus had first class interfaces to create testbenches that could map to UVM or verilator, it would be much more interesting. Spade does some interesting things by having its own package manager, but doesn't (afaik) expose a ton within the language itself
SUS ? Single UNIX Specification ?