Interesting but complementary foray into owning the end-to-end pipeline of chip design, fabrication, and packaging - especially for embedded use cases.
MIPS has also hitched it's horse to RISC-V now, and I am seeing a critical mass of talent and capital forming in that space.
MIPS seems like a story of missed (mipsed?) opportunities. If MIPS had really been (or remained) an open architecture, there would have been little need for RISC-V. They had a decade+ head start in terms of tool support and silicon implementation, compressed/16-bit instruction formats, full 64-bit instruction sets, and scaling from embedded systems to HPC.
6 comments
[ 3.1 ms ] story [ 21.6 ms ] threadMIPS has also hitched it's horse to RISC-V now, and I am seeing a critical mass of talent and capital forming in that space.
This could be interesting to see how much they try to loss-lead to get market share in the low-end
Is this the very beginning of a market consolidation?
https://en.wikipedia.org/wiki/Delay_slot
I'm surprised by how many other architectures use it.