Genuine question: the website doesn't work in Russia. Did you restrict the access or is it my ISP doing that? Someone tries to prevent me from studying of very niche info on ancient Intel CPUs. Thanks! P.S. Big fan of your work!
> From the circuitry on the die, this pin appears to be an output. If someone with a 386 chip hooks this pin to an oscilloscope, maybe they will see something interesting.
Would be a fun surprise if the 386 had its own Halt and Catch Fire mode.
It had ICE mode (precursor to SMM, but used for production testing and low-level debugging), and according to this article, the pins were exposed at least on some of the chips you could buy:
>On the standard Intel 80386 DX, asserting the undocumented pin at location B6 will cause the microprocessor to halt emulation and enter ICE mode.
[this is written from an ICE perspective - for "emulation", read "normal operation"]
This mode was introduced in the 80286, but I don't think the pins were exposed except in the special bond-out variant for ICE, and maybe early samples. You can trigger it in software (opcode 0F 04 on the 286, or by enabling a bit in DR7 on the 386), but then the processor disconnects from the bus and you have to reset it.
Hey @kens, congrats on the page! Extremely super small usability note/suggestion: if you changed your inputs (above the tool that lets you see all of the layers) to something like this:
then it would be possible to click the label name (i.e. Pins, I/O Vcc, etc.) instead of having to click the small radio circles.
It's a small thing, but I think it's a lot more fun/easy/fast to click the different label names rather than the circles. It's truly a small nit - just in case it's an easy fix for you. Cheers!
(just to make sure: you need to add a unique "id" attribute for each "input", and then make a <label> tag for each label referencing that id in the "for")
> (just to make sure: you need to add a unique "id" attribute for each "input", and then make a <label> tag for each label referencing that id in the "for")
Nesting the <input> inside the <label> is simpler. Then you don't need the id and for attributes. I think it avoids an unclickable space between them too.
A bit of a trip down memory lane for me. I performed an analysis of the thermo-mechanical cyclic fatigue in later packages using detailed CAD, FEA and empirical tests. A lot of work went into finding it wasn’t a big deal for the most part. Still, I don’t recommend that museums power cycle old PCs daily…
For museums, would it be an option to instead of a cooler have a temperature control unit that keeps the package at a set temperature no matter wether the PC is operating or not? Just heating the chips surfaces might be cheaper than having the full PC on 24/7 with a semi constant load.
Super cool! This was the CPU in my very first PC (which I got to build myself, under the tutelage of a family friend). I remember that it was cooled by nothing but a tiny stick-on heatsink and a small plastic fan that clipped on top of that.
8MB of DRAM, a 250MB spinning disk hard drive, 5.25 and 3.5 inch floppy bays, removable bios that I had to sort through a tupperware of chips to find the correct unit, some unnamed AGP video card that I had to slot removable chips into as well and a great big 16" CRT.
I think I had to install a special serial card in an ISA slot to use a mouse too.
The VGA cards often had a mouse port, I think. I don't recall having to add a serial card on 386s, but maybe we did. IBM machines were really oddball, too, with that fancier type of bus. I stayed away from IBM.
Went to a computer fair circa, gosh, 1989? My Dad bought me a 386 DX 25MHz with like 4MB of RAM and a whopping 40MB hard drive. This was a remarkable upgrade from the Tandy 286 16MHz that I was using. The 386 we got was not the standard 20MHz or 33MHz, 25MHz was some kind of hype thing, as I recall. The 33MHz was the bomb, but of course that cost more bones $$$$. The computer fairs were cool.
That lower level "Signals" CT image (layer 2) would have been an amazing background for the "Intel Inside" logo stickers. It has the proper era aesthetic and everything.
Anyways.. this is what I really like about kens work.. the accidental discovery of beautiful structures while trying to answer abstract questions. Thanks for doing all this!
A20M# (F13) - when supported by motherboard you can L1 cache whole ram instead of leaving first 64KB uncached
FLUSH# (E13) - when supported by motherboard you dont have to use hacks and flush L1 on every DMA access. Hacks (BARB mode) seemed clever at the time until everyone had a Sound Blaster DMAing audio constantly invalidating cache while gaming.
RPLSET (C6) RPLVAl (C7)- L1 cache status debug outputs
SUSP# (A4) SUSPA# (B4)- suspend support, wakes on INT and NMI. Good for laptops.
>The surprising thing is that one of the No Connect pads does have the bond wire in place
Somehow Cyrix picked this particular pin (B12) for KEN# input (enable L1 cache) :O
>From the circuitry on the die, this pin appears to be an output
Meaning the _one_ NC pin Intel CPU actually wires, an output no less, Cyrix demands driven low to enable cache.
I'm just glad someone is putting hybrid packaging information in the public domain. The generalized background information is really helpful for engineers new to this very small area. This wiring is not as complex as the old military hybrids for sure. It may be six layers but there is only one monolithic.
The anecdote about the 16-pin religion and the reluctance to use more pins is so good. It's often assumed that (later) successful companies were always making fantastic decisions in the earlier days, when in reality there were a few bizarre and harmful assumptions that were holding it back and needed to be forced out in order for rationality to prevail.
The reluctance to use more pins is very understandable.
At the time, Intel was primarily a memory manufacturer, and they had vertically integrated the complete workflow for anything that could fit into a 16-pin DIP. Anything that didn't, required them to outsource testing and packaging, or purchase expensive new machines. When CPUs were still being pushed against the wishes of upper management ("A computer has only one CPU but lots of memory chips, so the memory is a better business"), it was a hard sell to invest lots of money for an uncertain market.
26 comments
[ 2.3 ms ] story [ 41.2 ms ] threadWould be a fun surprise if the 386 had its own Halt and Catch Fire mode.
https://www.rcollins.org/ddj/Jan97/Jan97.html
>On the standard Intel 80386 DX, asserting the undocumented pin at location B6 will cause the microprocessor to halt emulation and enter ICE mode.
[this is written from an ICE perspective - for "emulation", read "normal operation"]
This mode was introduced in the 80286, but I don't think the pins were exposed except in the special bond-out variant for ICE, and maybe early samples. You can trigger it in software (opcode 0F 04 on the 286, or by enabling a bit in DR7 on the 386), but then the processor disconnects from the bus and you have to reset it.
On the 286, you can get it to dump some otherwise hidden internal state, by using a prefix that no longer exists on 386s: https://rep-lodsb.mataroa.blog/blog/intel-286-secrets-ice-mo...
It's a small thing, but I think it's a lot more fun/easy/fast to click the different label names rather than the circles. It's truly a small nit - just in case it's an easy fix for you. Cheers!
(just to make sure: you need to add a unique "id" attribute for each "input", and then make a <label> tag for each label referencing that id in the "for")
Nesting the <input> inside the <label> is simpler. Then you don't need the id and for attributes. I think it avoids an unclickable space between them too.
8MB of DRAM, a 250MB spinning disk hard drive, 5.25 and 3.5 inch floppy bays, removable bios that I had to sort through a tupperware of chips to find the correct unit, some unnamed AGP video card that I had to slot removable chips into as well and a great big 16" CRT.
I think I had to install a special serial card in an ISA slot to use a mouse too.
This one? https://en.wikipedia.org/wiki/Micro_Channel_architecture
Anyways.. this is what I really like about kens work.. the accidental discovery of beautiful structures while trying to answer abstract questions. Thanks for doing all this!
and Cyrix 486DLC hijacks 7 of those :)
A20M# (F13) - when supported by motherboard you can L1 cache whole ram instead of leaving first 64KB uncached
FLUSH# (E13) - when supported by motherboard you dont have to use hacks and flush L1 on every DMA access. Hacks (BARB mode) seemed clever at the time until everyone had a Sound Blaster DMAing audio constantly invalidating cache while gaming.
RPLSET (C6) RPLVAl (C7)- L1 cache status debug outputs
SUSP# (A4) SUSPA# (B4)- suspend support, wakes on INT and NMI. Good for laptops.
>The surprising thing is that one of the No Connect pads does have the bond wire in place
Somehow Cyrix picked this particular pin (B12) for KEN# input (enable L1 cache) :O
>From the circuitry on the die, this pin appears to be an output
Meaning the _one_ NC pin Intel CPU actually wires, an output no less, Cyrix demands driven low to enable cache.
Pedantic note: I think "quadratically" makes more sense here: we're talking about two dimensions.
At the time, Intel was primarily a memory manufacturer, and they had vertically integrated the complete workflow for anything that could fit into a 16-pin DIP. Anything that didn't, required them to outsource testing and packaging, or purchase expensive new machines. When CPUs were still being pushed against the wishes of upper management ("A computer has only one CPU but lots of memory chips, so the memory is a better business"), it was a hard sell to invest lots of money for an uncertain market.