It seems here that Google provides the core IP, and that Synaptic packages this (and probably other related IP blocks) block that can be used to build a SoC. As of now there are no chips announced. So it will be some years before we as software/electronics engineers get to play with it.
The architecture seems to be RISC-V array with standard RVV vector instruction set. That is a quite familiar environment for software developers compared to custom systolic arrays.
That's cool, any success stories, challenges or other feedback you can share?
I've only heard of people using Coral PCIe / USB for edge image AI processing tasks like classifying subjects in a stream. Curious if you have the same use case or something different!
Google's track record of suddenly dropping something they have developed and their stellar record on privacy make me pretty wary of this. I would like something like it, but Google as the champion just doesn't give me confidence.
I'm guessing you can still find Coral TPU-based boards somewhere but not sure what the support for these will be now that the focus is shifting. Coral TPU also uses subset of tensorflow and its nice to see that the open standard is targeting jax and torch.
> A core principle of Coral NPU is building user trust through hardware-enforced security. Our architecture is being designed to support emerging technologies like CHERI, which provides fine-grained memory-level safety and scalable software compartmentalization. With this approach, we hope to enable sensitive AI models and personal data to be isolated in a hardware-enforced sandbox, mitigating memory-based attacks.
This seems like important work and at first I wondered what this does for Google's bottom line. However reading about the simulator for software dev and the hardware kits, Google is aiming to win the AI glasses, etc. edge wars. All makes sense.
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[ 3.3 ms ] story [ 38.3 ms ] threadThe architecture seems to be RISC-V array with standard RVV vector instruction set. That is a quite familiar environment for software developers compared to custom systolic arrays.
Please language troll somewhere else.
someone at ycombinator should create a "github for silicon IP" company. that would be awesome.
I've been experimenting with the BeagleY-AI to build a little edge AI gizmo with a camera (Texas Insturments SoC + 4 TOPS NPU in RPi 5 form factor)
https://docs.beagleboard.org/boards/beagley/ai/demos/using-e...
I've only heard of people using Coral PCIe / USB for edge image AI processing tasks like classifying subjects in a stream. Curious if you have the same use case or something different!
When I went to see if anyone is selling the boards or their "Partners" page regarding manufacturing design I got 404 even after signing in: https://developers.google.com/coral/guides/coral/resource
> Hardware-enforced privacy
> A core principle of Coral NPU is building user trust through hardware-enforced security. Our architecture is being designed to support emerging technologies like CHERI, which provides fine-grained memory-level safety and scalable software compartmentalization. With this approach, we hope to enable sensitive AI models and personal data to be isolated in a hardware-enforced sandbox, mitigating memory-based attacks.