> Rather than allowing heat to build up, what if we could spread it out right from the start, inside the chip?... To do that, we’d have to introduce a highly thermally conductive material inside the IC, mere nanometers from the transistors, without messing up any of their very precise and sensitive properties. Enter an unexpected material—diamond.
> ... my research group at Stanford University has managed what seemed impossible. We can now grow a form of diamond suitable for spreading heat, directly atop semiconductor devices at low enough temperatures that even the most delicate interconnects inside advanced chips will survive... Our diamonds are a polycrystalline coating no more than a couple of micrometers thick.
> The potential benefits could be huge. In some of our earliest gallium-nitride radio-frequency transistors, the addition of diamond dropped the device temperature by more than 50 °C.
The article and paper don't mention it, but the thermal conductivity of single crystal diamond can be increased another 50% at room temperature by using pure carbon-12. The isotopic uniformity reduces scattering of phonons, which are what transports heat energy in diamond. For a very thin film like this the cost of using isotopically purified carbon shouldn't be that bad.
BTW, the thermal conductivity of C-12 diamond at cryogenic temperature is even higher, reaching something like 41000 W/m K at 104 K.
Isotopically purified silicon has also been considered due to its higher thermal conductivity, but the effect there at room temperature is not nearly as dramatic.
Weirdly, I read UV damage in C-12 diamond is reduced by a factor of 10 vs. natural diamond, I understand because this damage process is mediated by phonons. No relevance to the chip use case (unless UV damage in photolithography could be important?), but I found it interesting.
I joked about it last year[0], but before going for isotopically pure diamond they first have to make them single-crystal, the grain boundaries are worse than isotopic impurities.
If this can enable practically unlimited 3D stacking of CMOS layers, it could be hugely consequential for computing.
On an unrelated note, I like the writing style of this article a lot. This is how science journalism should be. It reminds me of how Scientific American used to be before it was ruined. Is IEEE Spectrum always like this? I might have to subscribe to the print version. I want articles like this floating around my house for my kids to discover.
Even according to the article: "2,200 to 2,400 watts per meter per kelvin - roughly six times as conductive as copper.". It's way higher than copper in fact. Copper is ~400 W/(m·K)
I can't wrap my head around possible yields, as the method relies on diamond crystals forming in the heat-conducting pillars within the chip, so if the process less than perfect - it can be a source of delayed failure from termal issues within the chip. It also look like a heat-conducting grid would further decrease usable space and the whole wafer needs to be designed around it.
That said, mentioned temperature gains are absolutely and utterly insane even if they come with some high-frequency issues.
> There are hurdles still to overcome. In particular, we still have to figure out a way to make the top of our diamond coatings atomically flat.
Not sure I understand this. Is this a requirement for real-world use? What happens if the outside of the coating isn't atomically flat? What makes this hard to do?
All semiconductor manufacturing techniques are based upon precisely flat layers of material that can be stacked and/or drilled into to produce a useful design. All vertical irregularities propogate to the layers above and can cause thinner layers when an upper layer is milled flat
Assuming this becomes easier and cheaper to do as the technique matures, a different use of this could be to help with cooling solar PV cells. Despite it being desirable (in terms of overall energy output) to put solar panels in places where the sun's energy is felt the strongest, solar panels tend to work the most efficiently when they're cool. By making it easier to efficiently cool solar PV cells, it may help provide a small boost in overall solar output.
If this can be scaled up, I wonder how useful it would be for use in space for radiative cooling - clearly, you can see I’m thinking of diamond skinned space-craft hulls - how cool is that!
I think cooling in a chip vs cooling in space are two orthogonal problems. In a chip, the problem is getting the heat to the heatsink where it can be efficiently dissipated into the much larger heatsink of the surrounding environment. In space, the problem is that the only way to dissipate heat is thermal radiation because you're in a vacuum.
No longer in that industry, but I worked on one of the first generation of semiconductor equipment for production when GAN first started picking up. Took about a decade before we saw it prevalent in consumer electronics. While this is interesting, I don’t see why DLC process won’t do something similar to this paper?
15 years ago a friend of mine was doing his PhD in laser physics and he was using diamonds to make a component cool faster. So the idea may be new in the chips space, but not new in general.
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[ 2.4 ms ] story [ 62.6 ms ] threadWhen it matures, you’re right back to the same heat constraint considerations, just with faster chips.
> Rather than allowing heat to build up, what if we could spread it out right from the start, inside the chip?... To do that, we’d have to introduce a highly thermally conductive material inside the IC, mere nanometers from the transistors, without messing up any of their very precise and sensitive properties. Enter an unexpected material—diamond.
> ... my research group at Stanford University has managed what seemed impossible. We can now grow a form of diamond suitable for spreading heat, directly atop semiconductor devices at low enough temperatures that even the most delicate interconnects inside advanced chips will survive... Our diamonds are a polycrystalline coating no more than a couple of micrometers thick.
> The potential benefits could be huge. In some of our earliest gallium-nitride radio-frequency transistors, the addition of diamond dropped the device temperature by more than 50 °C.
https://www.powerelectronicsnews.com/diamond-semiconductors-...
Edit: Because they are polycrystalline, and produced with a very new and novel technology.
"Our diamonds are a polycrystalline coating no more than a couple of micrometers thick."
BTW, the thermal conductivity of C-12 diamond at cryogenic temperature is even higher, reaching something like 41000 W/m K at 104 K.
Isotopically purified silicon has also been considered due to its higher thermal conductivity, but the effect there at room temperature is not nearly as dramatic.
Weirdly, I read UV damage in C-12 diamond is reduced by a factor of 10 vs. natural diamond, I understand because this damage process is mediated by phonons. No relevance to the chip use case (unless UV damage in photolithography could be important?), but I found it interesting.
[0] https://news.ycombinator.com/item?id=39742447
On an unrelated note, I like the writing style of this article a lot. This is how science journalism should be. It reminds me of how Scientific American used to be before it was ruined. Is IEEE Spectrum always like this? I might have to subscribe to the print version. I want articles like this floating around my house for my kids to discover.
If a chip were to be stacked as tall as it was wide, are we talking 10x, 100x, 100,000x?
I guess for N stacks you're still paying N chips worth of wafer, and Nx the amount of defects.
That said, mentioned temperature gains are absolutely and utterly insane even if they come with some high-frequency issues.
"Oxygen-assisted monodisperse transition-metal-atom-induced graphite phase transformation to diamond: a first-principles calculation study"
I think it's pay-walled unfortunately. https://pubs.rsc.org/en/content/articlelanding/2024/ta/d4ta0...
Not sure I understand this. Is this a requirement for real-world use? What happens if the outside of the coating isn't atomically flat? What makes this hard to do?
I confess to being a nerd that appreciates this “joke”
I don’t want to get my hopes up like graphene did and then get disappointed again.
Next, a diamond layer every few layers in 3D chips?
[1] https://www.alibaba.com/product-detail/Thermal-Management-Gr...
Are diamond blankets necessary for cooling graphene semiconductors, which are much less thermally wasteful?