Instruction pipelining and this is exactly why I wish we still have the time to go back to "it is exactly as it is", think the 6502 or any architecture that does not pretend/map/table/proxy/ringaway anything.
That, but a hell lot of it with fast interconnect!
Do you want to throw out out-of-order-execution and pipelining while you are at it, too?
I'm semi-serious: there are actually modern processor designs that put this burden on the programmer (or rather their fancy compiler / code generator) in order to keep the silicon simple. See eg https://en.wikipedia.org/wiki/Groq#Language_Processing_Unit
I don't know if this is just me being paranoid, but every time I see a phrase like this in an article I feel like it's co-written by an LLM and it makes me mad...
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[ 5.6 ms ] story [ 24.1 ms ] threadThat, but a hell lot of it with fast interconnect!
... one can always dream.
I'm semi-serious: there are actually modern processor designs that put this burden on the programmer (or rather their fancy compiler / code generator) in order to keep the silicon simple. See eg https://en.wikipedia.org/wiki/Groq#Language_Processing_Unit
I don't know if this is just me being paranoid, but every time I see a phrase like this in an article I feel like it's co-written by an LLM and it makes me mad...