> So when the opportunity arose to join an experimental shuttle using global foundries 180nm for FREE I jumped onto the opportunity and designed my own JTAG!
The thing I love about blog posts like these is how it reminds me that the tech world is a vast ocean that encompasses so many disciplines; it's not all full stack web development.
Related: I did not understand 95% of what she wrote.
Out of curiosity, does anyone know how many of the tools involved in the Tiny Tapeout project are available open source?
Especially in the project roadmap section..
The licences for proprietary EDA tools are very expensive it seems and most EDA people i talked to didn't really care for any open source tools - as their companies paid for the licenses.
Incredible dive into something I’ve only dreamed of doing, this post is definitely one of my favorites. If the author is reading this, would love to know where you got those chairs!
I've probably worked on 70 chips over the last 30 years.
Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes.
Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software.
When you combine it with a fixed shuttle date like in the article it is even worse because if you miss that date it might be another 1-2 months for the next shuttle instead of just a day for day slip when you control all the masks.
I'm shocked that SRAMs would be considered a luxury item for open silicon. They're essential for building anything that would be commercially viable, since area is far from free.
As someone who isn’t familiar with the deep details of the hardware side of the AI industry, I’m curious if these chips are “easy” to write AI software for, or if there is a big barrier. How significant is Nvidia’s moat on the software layer, which I often see talked about in articles, when people seem to be willing to adopt AI accelerators. And if AI accelerators can be adopted, why aren’t other competitors to Nvidia (AMD, Intel, etc) able to break in?
As a person that is using Librelane daily in their workflow, why did they skip Gate-level simulation? Iverilog won't ensure the circuit works after tapeout, CVC most likely will.
SDF-annotated simulation actually shows data hazards, as well as transistor timings.
> Once again, I used Cocotb as the abstracting layer allowing me to interface with multiple different simulators. Namely, icarus verilog for my standard verification and CVC for the post implementation timing annotated netlist.
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[ 5.2 ms ] story [ 42.6 ms ] threadIn case anyone wants a preview of what to expect.
Related: I did not understand 95% of what she wrote.
Especially in the project roadmap section..
The licences for proprietary EDA tools are very expensive it seems and most EDA people i talked to didn't really care for any open source tools - as their companies paid for the licenses.
I love the writing style!
https://tinytapeout.com/chips/tt05/tt_um_rejunity_sn76489
https://tinytapeout.com/chips/tt07/tt_um_rejunity_ay8913
https://tinytapeout.com/chips/tt04/tt_um_morningjava_top
Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes.
Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software.
When you combine it with a fixed shuttle date like in the article it is even worse because if you miss that date it might be another 1-2 months for the next shuttle instead of just a day for day slip when you control all the masks.
https://librelane.readthedocs.io/en/latest/usage/timing_clos...