I'm the author. The 5500FP is a complete 24-trit balanced ternary RISC
processor implemented on an Efinix Trion T20F256 FPGA, with a custom
open hardware development board (GargantuRAM).
The ISA is fully documented, including instruction formats, privilege
model, and a trit-based data hierarchy.
I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary?
Is there a compiler?
How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA?
2 comments
[ 2.5 ms ] story [ 15.0 ms ] threadThe ISA is fully documented, including instruction formats, privilege model, and a trit-based data hierarchy.
Full ISA docs and hardware at https://www.ternary-computing.com/docs/assembly/ISA/doc_inde...
Mainboard OpenHardware: https://github.com/Ternary-Computer-System/GargantuRAM Very simple OS: https://github.com/MOS5500/GRam_OS
Happy to answer questions on this architecture.
The first question has to be: why?
I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary?
Is there a compiler?
How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA?