Beware. I had Claude code with opus building boards and using spice simulations. It completely hallucinated the capabilities of the board and made some pretty crazy claims like I had just stumbled onto the secret hardware billion dollar project that every home needed.
None of the boards worked and I had to just do the project in codex. Opus seemed too busy congratulating itself to realize it produced gibberish.
Hit this exact wall six months back building Claude Code stuff for KiCad review[1]. First pass let Claude read .kicad_sch directly via grep/read. It happily invented pin numbers that didn't exist. Rewrote it with Python analyzers that spit out JSON, now Claude just reads the JSON, problem mostly went away.
Curious how spicelib-mcp handles models that aren't in the bundled library. Do you pass the .lib path as a tool arg, or does the server own a registry?
Different domain but similar pattern — I hit a related wall building an MCP server for Claude Desktop (Obsidian-based memory system). Not a registry question, but adjacent: how much state the server should own vs. pass through.
The thing that bit me hardest wasn't architectural though, it was a hardcoded 60-second tool call timeout in the MCP SDK used by Claude Desktop. app.asar confirms it — no config knob to raise it. For any long-running tool (mine: extracting and summarizing a 50-page PDF) the only option is detached spawn: Phase 1 kicks off work and returns "queued" within 60s, Phase 2 runs fire-and-forget and writes results to disk for a later kioku_list call to pick up.
If your server ever does work that might exceed ~45 seconds on Desktop, worth designing that in early. Claude Code's CLI doesn't have this limit, but Desktop users will hit it.
Really nice. My mother is an applied Physics teacher, and she told me they had a hard time at work figuring out how they could connect their teaching material to LLM in a relevant way. This should be useful to her.
I mean yeah FPAA’s would be awesome and I used to wish for something like it coming from a discrete analog hobby electronics.
But in a my short two years in Analog IC design industry, i have been so divorced from the actual silicon that I rarely got a chance yet to go in lab and probe around the teeny tiny block I worked on in the complex labyrinth of the SoC. I don’t wish for it (I learnt the hard way, be careful what you wish for; and in this case, if I am in lab debugging something in silicon, means something terrible has happened to what I worked on and it might have cost the company about $200k or more), but someday soon i will get into the lab just to play around with the fancy ass oscilloscope.
In the meanwhile, I did realize the invaluable power of having a python frontend API for querying basic details of your devices. (Python and not SKILL/Lisp since it pretty much works with any AI, and is very well worked on) and AI has been okayish with it. I feel AI would be a good aid in actual circuit design if it understood the Topology of the circuit, which at this point I am tempted to say might require something akin to AST but for SPICE. However, AI has been awesome at regexes and scripting which is also the meh and boring part of the circuit design process.
The AST idea for spice is something i've thought about too. a netlist is already a graph, the LLM just can't see it that way when it's flat text. serializing it with topology intact, adjacency, port polarities, device semantics is basically what your python frontend is doing implicitly, which explains why it behaves so much better than dumping a raw netlist into the prompt.
This is an interesting use case with Claude. It sounds like you took away some tedious work with the checking of waveforms, and you are able to speed up your design loop because of it.
Nice scope!
I had a similar experience with using Claude to automate circuit design/simulation/optimization and found that they are not good at it.
They are surprisingly good at taking raw files and describing what is in them, but they fall apart when trying to do anything other than design the simplest circuit. I think it is because they have no concept of the physics behind a circuit, so they cannot make changes that a designer would make. For optimizing a circuit using, say, an EM simulator, they don't know what to tweak and how to tweak it. In the end, I had to write a script to talk to the simulator and create a config file that specified the bounds of the simulation: step size, optimization algorithm, min, max, etc. Only then could I use an agent to call the script to optimize the circuit.
What I like here is the shift from better prompts to better feedback. With SPICE and scope data in the loop, it can actually iterate instead of guessing. The file based approach is also a small detail that makes a big difference in practice
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[ 2.4 ms ] story [ 45.1 ms ] threadNone of the boards worked and I had to just do the project in codex. Opus seemed too busy congratulating itself to realize it produced gibberish.
Curious how spicelib-mcp handles models that aren't in the bundled library. Do you pass the .lib path as a tool arg, or does the server own a registry?
[1] https://github.com/aklofas/kicad-happy
The thing that bit me hardest wasn't architectural though, it was a hardcoded 60-second tool call timeout in the MCP SDK used by Claude Desktop. app.asar confirms it — no config knob to raise it. For any long-running tool (mine: extracting and summarizing a 50-page PDF) the only option is detached spawn: Phase 1 kicks off work and returns "queued" within 60s, Phase 2 runs fire-and-forget and writes results to disk for a later kioku_list call to pick up.
If your server ever does work that might exceed ~45 seconds on Desktop, worth designing that in early. Claude Code's CLI doesn't have this limit, but Desktop users will hit it.
1: https://en.wikipedia.org/wiki/SPICE
waiting for FPAA to get better so we can vibecode analog circuits
https://www.eetimes.com/podcasts/making-analog-chip-designs-...
But in a my short two years in Analog IC design industry, i have been so divorced from the actual silicon that I rarely got a chance yet to go in lab and probe around the teeny tiny block I worked on in the complex labyrinth of the SoC. I don’t wish for it (I learnt the hard way, be careful what you wish for; and in this case, if I am in lab debugging something in silicon, means something terrible has happened to what I worked on and it might have cost the company about $200k or more), but someday soon i will get into the lab just to play around with the fancy ass oscilloscope.
In the meanwhile, I did realize the invaluable power of having a python frontend API for querying basic details of your devices. (Python and not SKILL/Lisp since it pretty much works with any AI, and is very well worked on) and AI has been okayish with it. I feel AI would be a good aid in actual circuit design if it understood the Topology of the circuit, which at this point I am tempted to say might require something akin to AST but for SPICE. However, AI has been awesome at regexes and scripting which is also the meh and boring part of the circuit design process.
Ye'ol poop splatter (Claude) is getting worse, more expensive, and anti-user. Local may be slower, but it is where the future of LLMs are going to.