I thought this was going to mean each stack was able to directly talk to the controller, since all stacks are resting on an interposer thing. But actually there is still a logic controller slice at the bottom of the stack, not at a right angle to the stack.
Instead of HBM microbumps between layers there is a more compact/dense TSV ("fusion bonded via-in-one") system. Intel once more showing their strong chiplet packing prowess! The claim is that thermals are still much better somehow, in spite of volumetric cell density increasing (from thinner layers). The demo has 8+1 dram+controller layers.
A search for patents by Stephen Morein who is listed as the CTO of SAIMEMORY shows
this one, assigned to Intel, and published strangely close to the press release;
That slide is wrong, it's stacked the same way HBM is, the key difference is that they don't use microbumps anymore and instead have a hybrid bond system using copper to copper bonding. Copper is a good thermal conductor and the via is going through the entire wafer which in turn means that they are forming an uninterrupted copper cylinder that goes through all the layers. It's as if they put heat pipes inside the chip.
This is not a drastically different technology like optane - it's almost solely a packaging change. It's applicable to exactly the same markets as normal DRAM, so if it dies customers will just switch to whatever DRAM variant wins instead.
Intel does these "throw spaghetti on the wall" kind of investments into potientially interesting companies/technologies all of the time - and have done so for decades.
Every time the recipient hypes the shit out of it, of course.
I have a feeling this will go the way of Optane and once it becomes useful they'll pull it and shelve it while keeping the patents/license of course so no one else can improve on it
One can only imagine how much money Intel would have made from Optane during the ongoing RAM shortages. It would be absolutely perfect for warm KV cache, and potentially good for MoE expert offloading.
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[ 3.2 ms ] story [ 35.2 ms ] threadI thought this was going to mean each stack was able to directly talk to the controller, since all stacks are resting on an interposer thing. But actually there is still a logic controller slice at the bottom of the stack, not at a right angle to the stack.
Instead of HBM microbumps between layers there is a more compact/dense TSV ("fusion bonded via-in-one") system. Intel once more showing their strong chiplet packing prowess! The claim is that thermals are still much better somehow, in spite of volumetric cell density increasing (from thinner layers). The demo has 8+1 dram+controller layers.
https://patents.google.com/patent/US20260040969A1/en
It talks there about 'Z axis memory' rather than angle, and that one is talking about inductive stuff through stacks of vias.
he's also got: https://patentsgazette.uspto.gov/week02/OG/html/1542-2/US125...
He obviously likes thinking about stacks of dies.
https://www.appliedmaterials.com/us/en/semiconductor/markets...
Edit: According to some rumors, the copper pillars go diagonally through the Z-Angle Memory.
Every time the recipient hypes the shit out of it, of course.
Get perpendicular: https://www.dailymotion.com/video/x62mja