The Z80 spawned the 64180 which was a Z80 with loads of stuff built in (from Wikipedia)
Execution and bus access clock rates up to 10 MHz
Memory Management Unit supporting 512K bytes of memory (one megabyte for the HD64180 packaged in a PLCC)
I/O space of 64K addresses
12 new instructions including 8 bit by 8 bit integer multiply, non-destructive AND and illegal instruction trap vector
Two channel Direct Memory Access Controller (DMAC)
Programmable wait state generator
Programmable DRAM refresh
Two channel Asynchronous Serial Communication Interface (ASCI)
Two channel 16-bit Programmable Reload Timer (PRT)
1-channel Clocked Serial I/O Port (CSI/O)
Programmable Vectored Interrupt Controller
As a consequence it was really popular in the 90s as an embedded processor just when I was starting my career. This lead to me writing thousands of lines of Z80 assembly. You could program it in C but the compiler was useless at making stuff go fast.
One of those things I wrote was an LZ77 decompressor used in a satellite broadcast system. It took me about a week to write it, test it and optimise it. Quite a challenge! I remember optimising it about the LDIR instruction to copy memory.
The compressor was written in C and ran on the PCs of the day.
I come from the same lineage as the author. I did 6502 (doing C64 demos) long before I encountered the Z80. From what I remember, the Z80 offers a vastly superior programming experience. It has more registers. it has 16 bit registers. It has a shadow register set (you can switch between sets, which is handy for interrupt routines, for example) Programming assembly on the Z80 just is less of a fight.
There's also the weird more than an 8080 but not quite a Z80 CPU in the Gameboy (which Sharp seem to call an SM83 when they used it in their microcontrollers).
I find programming for the 6502 to be a joy in a way that the Z80 isn't. I'm not quite sure why that is; I guess maybe because 6502 feels so stripped down, the amount of context you have to keep in your head is extremely low?
I could hold the whole 6502 instruction set (and their cycles) in my mind while programming, it was that simple.
I acquired a Z-80 softcard for my Apple ][ (for trying out CPM) and was flabbergasted by the expanded register set, the complexity of some instructions (e.g. DJNZ) and the fact it ran at 4MHz vs 1MHz for the 6502 (got a speed demon 65C02 card later). However I couldn't keep all instructions and timings in my head. Speedwise the 1MHz 6502 and 4MHz Z80 were on par.
I preferred, however, the fact that I/O was memory mapped on the 6502.
> Speedwise the 1MHz 6502 and 4MHz Z80 were on par.
This is a bit of an exaggeration, the 6502 was efficient but not that efficient. While generally understood that the Z80 took 2x-4x ticks to execute instructions as the 6502, in the real world its larger register set meant properly-written Z80 code could avoid expensive, slow round trips to memory.
Outside of artificial benchmarks real world performance shows that the 6502 is roughly 2x as efficient per clock cycle as the Z80[0], i.e. a 1 MHz 6502 is approximately equivalent to a 2 Mhz Z80.
This is reflected in the computers of the day, i.e. TRS-80s were not being blown out of the water by Commodore PETs.
> I preferred, however, the fact that I/O was memory mapped on the 6502.
The Z80 could do memory mapped IO as well of course (used at least in some arcade machines), but why waste valuable address space when there's an entire 64 KB of extra address space reserved for IO ;)
I'm a 6502 guy myself, but the Z80 instruction set is also easily holdable in one's memory.
As others said, a 4MHz Z80 is clearly capable of outperforming a 1MHz 6502 as is evidenced by the many ZX Spectrum demos that show off 3D/plotting effects.
> Less immediately visible to someone working at the assembly language level instead of the machine code one is that relative addressing is much more common on the 6809, meaning that it’s significantly more viable to write position-independent code on it than any of the other chips we’ve looked at here. Only the 8086 comes close, and it achieves it by using its segment registers as a de facto relocation base.
I would love to learn more about this. Does more "position-independent code" mean the linker has much less to do [0], or is there an actual difference in the code base for similar tasks?
"The 6809 saw some success, especially in arcade machines, but it did not steamroll the world the way the 6502 and Z80 did."
Could have mentioned the use of the 6809 in the Radio Shack TRS-80 Color Computer and the Dragon in the UK. Using the TRS-80 tag on something not using a Z-80 never made sense.
I admit that I did everything with a Z80, except for using one. Because the TRS-80 used a Z80, Radio Shack carried a book on it, published by Howard Sams. It was next on the shelf after the TTL book, so of course I bought it and devoured it without ever touching a Z80.
My impression of the Z80 being clean and simple probably resulted from that book being so clearly written. It gave me a good enough understanding of how micro's work, that lasted until the more modern chips came out with things like pipelining. But I think that learning one of those old 8 bit chips would still be a great place to start for understanding things at a hardware level.
As someone familiar with z80, 6502, and 68HC11 instruction sets this breaks down the key differences between the "6s" and "8s" archs well. I personally learned z80 first, then found the 6502 a bit limiting after writing z80 for a bit. That said, I still love writing bare metal 6502 for my Atari 2600's handicapped 6507 (missing an address line among a few other oddities). Sometimes limits are a good thing. I certainly would never want to remember all the more complex cisc instruction sets for example.
In 2025 I started programming 6502 assembly just for fun as intellectual exercise (i did TINY bit of x86 asm in the past) and MY GOD: this is so easy and so valuable to learn!
Programming 6502 seems simpler than learning lets say JS framework or to learn just about anything modern.
Its super fun, super easy and very rewarding.
I ended up designing my own ultra RISC, stack based and uniform 32-bit fixed-length data size (all instructions and data have exactly the same size) with mimo and other cool features. 6502 on steroids
I felt competent first time for long time as jobless programmer doing that :)
> I find [8086 segmentation] enormously preferable to the 65816’s bank system. The primary advantages are twofold: segment overrides may be provided to any pointer, which means that it is less necessary to juggle segment values the way it is necessary to juggle the 65816’s data bank pointer, and—even more crucially—the 8086 has two simultaneous data bank pointers (DS and ES), which allow accessing two “far” pointers simultaneously without any register juggling at all.
Juggling? Ouch! These comments reveal an apparent unawareness of the 65816's long address modes, which offer four different ways of computing a full, 24-bit address.
None of the long address modes involves the "data bank pointer" (Data Bank Register), which can more appropriately and less painfully be used for legacy code (6502) and other 64K-oriented contexts.
Two of the 65816's long address modes use three-byte indirect pointers in zero-page/Direct-Page, where any reasonable number of long pointers can be simultaneously available (in contrast to only DS ES CS SS). And segment override prefixes never come into the picture.
Finally, "hitting bank boundaries" is not the excruciating issue it's made out to be, because the indexed long modes transparently span said boundaries. And note that the 16-bit index is added to a fully specified 24-bit base (not a 16-bit base inflated to 20 by shifting zeros into the LSBs).
21 comments
[ 3.5 ms ] story [ 42.6 ms ] threadThank you!
Execution and bus access clock rates up to 10 MHz
Memory Management Unit supporting 512K bytes of memory (one megabyte for the HD64180 packaged in a PLCC)
I/O space of 64K addresses
12 new instructions including 8 bit by 8 bit integer multiply, non-destructive AND and illegal instruction trap vector
Two channel Direct Memory Access Controller (DMAC)
Programmable wait state generator
Programmable DRAM refresh
Two channel Asynchronous Serial Communication Interface (ASCI)
Two channel 16-bit Programmable Reload Timer (PRT)
1-channel Clocked Serial I/O Port (CSI/O)
Programmable Vectored Interrupt Controller
As a consequence it was really popular in the 90s as an embedded processor just when I was starting my career. This lead to me writing thousands of lines of Z80 assembly. You could program it in C but the compiler was useless at making stuff go fast.
One of those things I wrote was an LZ77 decompressor used in a satellite broadcast system. It took me about a week to write it, test it and optimise it. Quite a challenge! I remember optimising it about the LDIR instruction to copy memory.
The compressor was written in C and ran on the PCs of the day.
I acquired a Z-80 softcard for my Apple ][ (for trying out CPM) and was flabbergasted by the expanded register set, the complexity of some instructions (e.g. DJNZ) and the fact it ran at 4MHz vs 1MHz for the 6502 (got a speed demon 65C02 card later). However I couldn't keep all instructions and timings in my head. Speedwise the 1MHz 6502 and 4MHz Z80 were on par. I preferred, however, the fact that I/O was memory mapped on the 6502.
This is a bit of an exaggeration, the 6502 was efficient but not that efficient. While generally understood that the Z80 took 2x-4x ticks to execute instructions as the 6502, in the real world its larger register set meant properly-written Z80 code could avoid expensive, slow round trips to memory.
Outside of artificial benchmarks real world performance shows that the 6502 is roughly 2x as efficient per clock cycle as the Z80[0], i.e. a 1 MHz 6502 is approximately equivalent to a 2 Mhz Z80.
This is reflected in the computers of the day, i.e. TRS-80s were not being blown out of the water by Commodore PETs.
[0] https://github.com/soegaard/minipascal/blob/master/minipasca...
The Z80 could do memory mapped IO as well of course (used at least in some arcade machines), but why waste valuable address space when there's an entire 64 KB of extra address space reserved for IO ;)
As others said, a 4MHz Z80 is clearly capable of outperforming a 1MHz 6502 as is evidenced by the many ZX Spectrum demos that show off 3D/plotting effects.
I would love to learn more about this. Does more "position-independent code" mean the linker has much less to do [0], or is there an actual difference in the code base for similar tasks?
[0] https://sourceware.org/binutils/docs/ld/Overview.html
Could have mentioned the use of the 6809 in the Radio Shack TRS-80 Color Computer and the Dragon in the UK. Using the TRS-80 tag on something not using a Z-80 never made sense.
https://www.llvm-mos.com
My impression of the Z80 being clean and simple probably resulted from that book being so clearly written. It gave me a good enough understanding of how micro's work, that lasted until the more modern chips came out with things like pipelining. But I think that learning one of those old 8 bit chips would still be a great place to start for understanding things at a hardware level.
Dynamic memory refresh on chip was clever.
In 2025 I started programming 6502 assembly just for fun as intellectual exercise (i did TINY bit of x86 asm in the past) and MY GOD: this is so easy and so valuable to learn!
Programming 6502 seems simpler than learning lets say JS framework or to learn just about anything modern.
Its super fun, super easy and very rewarding.
I ended up designing my own ultra RISC, stack based and uniform 32-bit fixed-length data size (all instructions and data have exactly the same size) with mimo and other cool features. 6502 on steroids
I felt competent first time for long time as jobless programmer doing that :)
Juggling? Ouch! These comments reveal an apparent unawareness of the 65816's long address modes, which offer four different ways of computing a full, 24-bit address. None of the long address modes involves the "data bank pointer" (Data Bank Register), which can more appropriately and less painfully be used for legacy code (6502) and other 64K-oriented contexts.
Two of the 65816's long address modes use three-byte indirect pointers in zero-page/Direct-Page, where any reasonable number of long pointers can be simultaneously available (in contrast to only DS ES CS SS). And segment override prefixes never come into the picture.
Finally, "hitting bank boundaries" is not the excruciating issue it's made out to be, because the indexed long modes transparently span said boundaries. And note that the 16-bit index is added to a fully specified 24-bit base (not a 16-bit base inflated to 20 by shifting zeros into the LSBs).
Otherwise an interesting article -- I enjoyed it.