HN Explorer

Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator (github.com)

119 points by gdevic ↗ HN
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch.

The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.

What the project covers:

- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution FSM, hardware stack guard with a FAULT state for microcode debugging

- CORDIC for trig functions, verified to 14 significant digits

- Two-pass assembler in Python (~700 lines)

- Verilator + Qt framework: same Verilog source runs in simulation, as a desktop GUI debugger, as WebAssembly, and on real hardware

- Scripting language on top of the microcode for adding functions without touching hardware

- Custom PCB (EasyEDA/JLCPCB), battery, charging circuit

Write-up: https://baltazarstudios.com

Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the...

17 comments

[ 0.52 ms ] story [ 36.9 ms ] thread
[deleted]
(comment deleted)
VLM
Ironically the Z80 is a nibble ALU. That's why its so slow compared to the competition, an 8 bit add on a "2 MHz" Z80 takes as much clock time as a 8 bit add on a "1 MHz" 6809.
drob518
My dad worked for HP from the mid-1970s through the mid-1990s. Needless to say, I used HP calculators in high school and college. The best things about having an HP calculator were the solid physical construction (the buttons on the 11C and 15C were awesome), the accuracy, and the fact that whenever your classmates asked to borrow your calculator they would recoil in horror when you asked them whether they knew RPN. Nobody borrowed my calculator. Anyway, I love this project.
wewtyflakes
If the CPU is nibble-oriented, wouldn't that mean that that is its byte size?
djmips
At least the 6502 has a BCD mode built in!
mountain_peak
Very impressive, and obviously a labour of love! As a calculator and SystemVerilog enthusiast, it's wonderful to see a project such as this come to fruition - congratulations!

I'm holding in my hand a 4-bit Von Neumann Mostek MK50310N that my father and I used to use to build calculators long ago. Although Mostek made chips for HP (such as the HP-35), they weren't commercially available, but the 50310 was. We could only dream of a project such as yours. I was happy when the "open source" NumWorks was released, but this project aligns more with my interests.

Will definitely install the Qt simulator - would be even better to build one IRL!

fitsumbelay
Love this and love seeing people building their own hardware/software tools. I hope to carve out the time soon to be one. Calculators are a perfect project

are there videos available?

NetMageSCW
This is a brilliant project. (My DM42 returned 9 exactly.)

Blog post 6 had an error where the picture of a HP-71B (I have one and used its Forth/Assembler ROM manual to write the first HP-48 ROM decoder) where the caption says it is a 48GX (both used a Saturn CPU).

russdill
Cool project

Really hoping that ghidra can add support for non-byte aligned memory regions some day. So many cool 4-bit architectures out there and attempting to shoehorn them into ghidra produces not great results

random__duck
I wish I could give this project more respect than simply saying it is awesome and contraz.

Also, let us all hate on denomals! :)

wg0
It is... Unbelievably exciting project. There's a lot and lot learn and explore. I'll be reading all of it.