Honestly this is the first time I am seeing this kind of work that i genuinely like. Most fractal and other kinds of self repeating results are not that interesting at all to me.
Not really an HDL, as currently it has no concept of actually connecting the nodes. Each edge is an arbitrary number of conductors with no constraints on routing or timing. Curious to see where this goes though
The graphs are beautiful, however they're independent of the language (because they're a visualization of the resulting gates). You could get the same graphs from VHDL or Verilog.
I don't like the "fallback" mechanism, because it will be used when "something goes wrong", without being specific about exactly under what conditions should the fallback happen. Maybe I made a mistake, "something" fails at a step I didn't expect, and this will silently implement in a way I didn't mean (maybe the result is even correct, just using way more gates than needed).
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[ 4.0 ms ] story [ 27.2 ms ] threadIs this kinda similar in nature?
I don't like the "fallback" mechanism, because it will be used when "something goes wrong", without being specific about exactly under what conditions should the fallback happen. Maybe I made a mistake, "something" fails at a step I didn't expect, and this will silently implement in a way I didn't mean (maybe the result is even correct, just using way more gates than needed).