Scrying the AMD GFX1250 LLVM Tea Leaves (chipsandcheese.com)

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...not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache.

What is this feature for? When do you need it?

averne_ 1mo ago ↗

The explanation is missing that the hardware also notifies you of modifications, which makes it useful for implementing cross-cluster synchronization primitives.

Compare to MONITOR/MWAIT on x86: https://www.felixcloutier.com/x86/mwait#mwait-for-address-ra...

majke 1mo ago ↗

I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.

averne_ 1mo ago ↗

They already do, it's called v_bitop3_b32. Added in CDNA4, present in CDNA5 and will be making its way in RDNA5, if the LLVM code is to be trusted.

https://www.amd.com/content/dam/amd/en/documents/instinct-te...

androiddrew 1mo ago ↗

Where does someone start on kernel development for an RDNA4? Books, resources, whatever?

8 year developer just getting into to AI side of the house