Cool that you can make a NAND gate like this, but I was more hoping for something that showed how to practically (ab)use a video encoder for "great computational power" to do something real. Not just how to make a NAND gate with one.
Looks like VP8 has a max resolution of 16383x16383 pixels. Looks like minimum block size is 4x4 pixels, so 4096x4096 blocks, with maybe 7x7 blocks per gate, including some wiring, so maybe something like 500x500 logic gates?
I don't think we'll be running Doom, but you could definitely make a little CPU, with programs!
What is this math from? How do you suppose there to be less gates than pixels? Also, different implementations may unroll to different degrees, with some lower thruput hardware doing stuff sequentially by reusing the same logic
Funny this is how people initially started re-shaping some computational problems to resemble graphic pipelines and get "great computational power"; back when it was called GP(General Purpose-)GPU computing.
I was wondering whether there's any way to make wires "cross", which would be needed to construct a non-planar circuit. But even if there isn't a way to do this directly, Gemini tells me that it's possible to construct a planar circuit (built out of XORs which are themselves built out of NANDs) that effectively "crosses" two wires!
Mapping the abilities of (fixed-function) "stream transformers" to compute is old, much older than "GPU libraries" or render pipelines and all that. I remember the Commodore Amiga used the blitter's combine to decode/encode floppy data, but there are likely other examples predating that. In which sense is VP8 "different" there from another "fixed-function" processor?
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[ 4.0 ms ] story [ 25.2 ms ] threadI don't think we'll be running Doom, but you could definitely make a little CPU, with programs!