ABSTRACT
A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
Or AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
If we exclude short-term shortages then no. The cost to make a wafer hasn't really changed. Larger wafers improved costs but that's about it AFAIK.
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
I'm saying Fujitsu never made any real attempt to sell their product to anyone except very large companies with purchasing departments. Thus it is little wonder they never really got much in the way of sales.
Maybe that strategy works in Japan or Asia but it didn't work here and I think that's a shame because we could have used the competition.
The cost-per-transistor used to fall as density increased (Moore's Law), but has now basically flattened off.
As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ...
The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). If foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
I'll admit I am not well versed on this subject on any measure, but there is this [0] paper indicating FinFET is doable, although IDK if there's any sort of hand-waving or other limitations involved.
The reality is often going to be much worse than TSMC's N2 -> A14 20% density increase "mixed design" marketing spin.
Apparently the N2 -> A14 density increase for logic is 23% (Tom's Hardware), and about 0% for both SRAM and analog.
Both CPUs and GPUs devote considerable space to SRAM (registers & cache), and are 50% or less logic, so for them the density increase will more like 10% rather than TSMC's 20% marketing number.
20% growth then 20% again still seems pretty good to me though. I guess compounded that is a 44% increase N3 to A14 which also starts to look much better if you zoom out a bit. I mean 44% more density since a few years ago seems, if not massive, not insignificant, like you will definitely notice it.
Yes but considering N10 was fabricated with DUV lithography right before the shift to EUV I'm not sure how fair that comparison is. That being said the density scaling of N10 nodes compared to predecessors using the same lithography technique was much higher than we have seen since with the EUV nodes. Density scaling is the most meaningful comparison metric, but it doesn't take into account additional technology developments.
cat /usr/share/X11/locale/en_US.UTF-8/Compose | grep Å
<dead_abovering> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <o> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <asterisk> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <A> <asterisk> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <A> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
I was laughing at the expected expectation of universally working UTF-8 just because it's 2026 when I read that. Soooo many things just do not work with UTF-8 as expected. I'm looking at MS Excel with heavy side eye
IEDM is more or less the most prestigious conference on semiconductor devices. Hard to get a more reliable source than a TSCM-affiliated paper from IEDM.
I did find it funny recently when Huawei when talking about its folded logic say the Vertical Bonding Pitch's are every 15,000 angstroms. It is a very fancy way of saying an interconnect every 1.5 microns.
What's wild is that the mirrors used in the EUV machines are smooth to a level of deviation even smaller that the feature size of the gates being etched.
These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
I am curious about characteristics of transistors in modern chips (propagation time, resistances and capacitances, drive current). Can someone spill the details?
I tried to make some estimations: modern CPUs can work at 4 GHz, which is 250 ps/cycle. Modern CPUs allegedly can do 64-bit addition in that one clock cycle. Carry-lookahead adder requires a fat 63-input AND followed by fat 63-input OR for computing the carry for MSB, which can be implemented as 2×8 layers of 2-input gates or 2×3 layers of 4-input gates, or 2×2 layers of 8-input gates. Then you add the carry to the sum which requires a XOR which is probably like 2 layers of standard gates. Then you need to respect set-up time for the flip-flop, and account for a propagation inside it. A flip-flop (2 latches) is at least 2 layers of gates. So if we consider 4-input gates, the path would be 6 + 2 + 2 = 10 layers, and the propagation time for one gate should be 250÷10 ~ 25 ps.
Is that correct or not? Or the clock of CPU is limited by thermal limits and not by propagation time? Or there are some tricks that allow using slower transistors?
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[ 1431 ms ] story [ 1007 ms ] threadABSTRACT A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.
> provides up-to 50% area reduction and reduced power consumption by a factor ten
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
Maybe that strategy works in Japan or Asia but it didn't work here and I think that's a shame because we could have used the competition.
As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ...
The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
eDRAM isn't the same as 1T-SRAM, which isn't quite the same as 1T-1C SRAM...
But overall they run into the same problems that you mention; it's just too hard to get a capacitor in play.
There is Zeno Semi's Bi-SRAM, buuuut it hasn't seemed to catch on for one reason or another.
Looks cool, but isn't it by definition planar process-only, no FinFET for you?
[0] - https://ieeexplore.ieee.org/document/8614555
Apparently the N2 -> A14 density increase for logic is 23% (Tom's Hardware), and about 0% for both SRAM and analog.
Both CPUs and GPUs devote considerable space to SRAM (registers & cache), and are 50% or less logic, so for them the density increase will more like 10% rather than TSMC's 20% marketing number.
Many people don't know.
Not sure what this source is, but it looks sketchy.
These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
I tried to make some estimations: modern CPUs can work at 4 GHz, which is 250 ps/cycle. Modern CPUs allegedly can do 64-bit addition in that one clock cycle. Carry-lookahead adder requires a fat 63-input AND followed by fat 63-input OR for computing the carry for MSB, which can be implemented as 2×8 layers of 2-input gates or 2×3 layers of 4-input gates, or 2×2 layers of 8-input gates. Then you add the carry to the sum which requires a XOR which is probably like 2 layers of standard gates. Then you need to respect set-up time for the flip-flop, and account for a propagation inside it. A flip-flop (2 latches) is at least 2 layers of gates. So if we consider 4-input gates, the path would be 6 + 2 + 2 = 10 layers, and the propagation time for one gate should be 250÷10 ~ 25 ps.
Is that correct or not? Or the clock of CPU is limited by thermal limits and not by propagation time? Or there are some tricks that allow using slower transistors?
Please help me solve this puzzle.