Chip-hex:cost-benefit, energy efficiency and hexagonal (github.com) 1 points by Engineercom 24d ago ↗ HN
[–] aappleby 23d ago ↗ There's nothing real in that repo, just a 20k python file and bits of documentation - all AI generated.
[–] jleahy 23d ago ↗ Sadly diagonal wires aren’t allowed by the fabs (at least on layers that would be relevant here). [–] ahartmetz 23d ago ↗ As well as non-90° angles when dividing the wafer into chips, probably. Well, I was already thinking of tiling chiplets, which the README doesn't mention. [–] nlewycky 23d ago ↗ Not in an advanced process node, but if you're doing open PDK work then you can get 45 degree bends in poly and metal. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verif...
[–] ahartmetz 23d ago ↗ As well as non-90° angles when dividing the wafer into chips, probably. Well, I was already thinking of tiling chiplets, which the README doesn't mention.
[–] nlewycky 23d ago ↗ Not in an advanced process node, but if you're doing open PDK work then you can get 45 degree bends in poly and metal. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verif...
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