The overclock on the 4770K is crap if it can be pushed only to 4.4 on air. Interesting if the 4670K will have more headroom. And review on the integrated graphics. Why bother? It will be good enough for anything non gaming related and crap for everything gaming related just like the previous 2 generations.
I'm not sure of the sense in comparing a $129 AMD CPU to a $329 Intel CPU. Sure, they both have integrated graphics but the budgets of people building a system with these CPU's are going to be very, very different. It'd be silly to build a system with an i7 and no discrete GPU when you could use an i3 (or even a Pentium) and use the savings on video card.
Unless you play demanding videogames there is litte point to having a discrete videocard so it's still a valid comparison. That said I have a 2600k @4ghz and there does not seem to be any reason to even consider an upgrade which I find rather disappointing.
Agreed - I still have a Nehalem 875k and was thinking about an upgrade, but while this stuff is significantly better than mine, I don't think it's Significant Enough to go build a new computer right now.
The power savings might get me to upgrade my laptop though.
Can someone please shed some light on this relatively recent APU race? I understand it seems like a good idea for OpenCL, but when they increase their APU performance while actually stagnating their CPU performance I am just completely lost (as is the case with the i7-4770K).
What is the market for desktop CPUs where the desktop buyers don't also have dedicated video cards which can do a almost a magnitude better job than the APU?
>What is the market for desktop CPUs where the desktop buyers don't also have dedicated video cards which can do a almost a magnitude better job than the APU?
Small form factors, like the iMac or Mac mini. Apple is pretty influential in Intel's roadmap nowadays. See also how the next-gen mobile chipsets are getting more powerful onboard GPUs to drive Retina displays.
I hadn't seen that. There are lots of research oriented robotics projects that use Apple Mac Minis for compute power. You just bolt on a Mini and you have a standard environment to run computer vision, learning, or advanced path planning, communicating with the robot's own computers by UDP, for example. NUC could be a nice intermediate point between the Mini and full integration with the robot's own computers.
NUC is nice, I measure mine at less than 10 watt for "smash the CPU" tasks, small form factor, good alternative to ridiculously expensive options like car PCs. I found it's also voltage tolerant. It's rated at 19v but you can run it at much less (down to 15).
EDIT: it does go up to nearly 20 watts, depending, esp if you have the HDMI plugged in. Technically I think you can get more out of a NUC than a mini in terms of raw MIPs. They're PCs, not toys like RPI.
Thanks for the info. For the robotics use case I mentioned, having a high-performance system is important because the algos are demanding, so a RPI would not be very good.
We should be leveraging the APU compute engine in opengl and opencl tasks to get more performance out of the system (maybe not gl, since it took a decade for ATI/AMD and Nvidia to properly support just having 2 of the exact same card work in parallel).
In practice, with the advent of compute shaders and opencl, there is very little intense serial work that can't be done in parallel. My workflow nowadays is (using python as an example)
Slow? (assuming we know why it is slow and it isn't just maligned algorithmic complexity making something a runtime exponential where you can use a quadratic) -> Put it in C++. Still slow? -> Parallelize into tasks and put in a work threadpool (assuming there is a lot of this kind of work happening, else just numcores / X threads do stuff). Still slow? -> Port over to opencl (or if memory copies are unnecessary, opengl compute shaders) and keep the old implementation for backwards compatibility with systems lacking them.
GPUs yield a higher core density and are more efficient in certain situations. This appears to be where the arms race is in HPC these days. Every cpu maker is trying to be the first to cross the finish line with a general purpose GPU solution these days(with a traditional CPU strapped to it's back to run the os). Rumor has it that nvidia will have an arm platform soon. I'm sure Intel and AMD are afraid of this. They want to have something in the pipeline that is competitive before this happens.
The way the market is going these days, consumer devices will soon almost all be based around low power/small footprint solutions(e.g. atom, mobile, arm). Heck, it probably won't be too long before we start seeing some serious SOC solutions(what could a raspberry pi type device do in 2 years with a 4 or 6 core arm at it's core). So, that kills margins on the consumer market more or less. Or, well, at least it becomes a race to the bottom. What's left is enterprise and "the cloud", where efficiency and iops still rule. For these companies, CPU speed isn't a bottleneck, it's mostly core and io density. They simply want to run more jobs in a smaller space, not necessarily run the jobs faster. So engineering teams are starting to look very closely at GPUs as a means to get a huge improvement in core density for certain situations at the cost of having to rethink some of the software stack. Putting the GPU on the same die as the CPU makes a lot of sense from this perspective.
It'll be interesting to watch. If nvidia does have an arm platform in the works, they may win this race, though intel does have a huge advantage with being able to run multiple foundries at one. Part of me wants to believe that intel is capable of doing much more with their APU solutions, but are simply waiting until the future of the market is clearer. Once that happens, they may be able to beat everyone else simply by timing the market on newer designs(like how intel beat AMD after screwing up with itanium and P4).
Note: Having a low power SOC type solution is another side effect of all this, but I don't think that's the primary motivator for Intel's efforts here. Maybe for the atoms, but not this chip.
NVIDIA's ARM platform isn't a secret. They announced Project Denver years ago. Their latest roadmap has it scheduled for 2015. The only unknown is how wide a range of power+performance they will be targeting. Will they start by going after phones, tablets, workstations, servers, HPC?
It's not really a desktop processor; it's a laptop processor that's being reused for the desktop market. Gamers might prefer a GT0 configuration but I guess the market isn't large enough to justify it.
CPU doesn't matter on the desktop unless you're doing something wrong or interesting. Hint: if you're paying for your own CPU intensive thing, try "engineering sample intel xeon" on ebay.
If you can stand the sunk cost it's a LOT cheaper than AWS. Horses for courses YMMV etc.
I buy not-for-resale chips on a dodgy basis for fuzzing (MOAR VMS!) but on the whole, bucks per MIP, or MIPs per watt - who cares?
I think watts per unit of performance is most important, as long as the more energy-efficient CPU isn't exhorbitantly more expensive, since we only pay for the hardware itself once but pay for energy continually.
I guess it depends on how much oomph you really need, but the e3-1230 v2 xeon is a tremendous processor (9k passmark) and can be had for the low $200s.
(x as many as I could afford). That does look like a good chip, but dodgy engineering sample trays in 2013 you can prolly get twice as many cores. That means NO WARRANTY and like, not for work.
Personally what I consider more interesting than the actual engineering sample chips is the "NDA" Preliminary Specification Updates that describes errata in these chips including steppings dating back to A0. Wonder if they are NDA after the product launched?
Stepping is a big deal if you're in the NFR (not for resale) market because it often hugely changes the power envelope. However, I don't generally pay attention to the exact instruction level changes because I'm not recompiling for it. I'm not given a manual, and often the seller is e.g. a "textile manufacturer" in China. Lol.
Perhaps you could find the microcode key ;) I've had hex-cores for nearly 2 years for 500 bucks each. It varies. You have to know who has a tray of stuff they want to get rid of. That's what makes you the kind of weirdo who risks a couple grand on random ebay xeons.
Is comparing a hex-core to a quad-core apples to apples? Haswell per core performance is still better although it will be a long time before we see a hex-core part.
Absolute performance isn't everything. The ratio of power consumption to performance is also important. In some cases, so is keeping maximum power consumption and/or heat dissipation under a certain threshold. But it looks like the i7-4770K falls behind the 3770K on power consumption, so I'm a bit disappointed too.
Power concerns are not common among the people that buy K processors. And for stable overclock disabling the C-states is usually a good starting point.
The 3930k is not in the same category as the just released Haswell processors. SB-E is designed for the top end premium performance and extreme categories whereas the just released haswell processors are in the low end premium performance to mainstream performance categories. The upcoming replacement for the SB-E processors is IB-E, the haswell offerings were never designed to replace SB-E.
Not to mention the 3930k has 6 cores whereas all of those have 4.
I really want to see benchmarks for scientific / math-heavy workloads. AVX2 & FMA3 are supposed to give double the peak FP & integer vector performance.
Unfortunately, it takes time to optimize code for each new architecture, and most benchmarks don't even bother with a recompile.
I don't even know the CPU flag to specify to go "I have the absolutely latest CPU". Generally all the scientific libraries have vectorised asm for the tight loop stuff. So what is a benchmark person gonna do?
-march=native at least. Something like re-tuning ATLAS at best.
Not really griping that much; eventually people do do those kinds of benchmarks, but they do take time, and they're not really the target audience for someplace like Tom's. Understandable they would focus on gaming & general-use benchmarks.
Thanks; I have to admit I didn't know -march=native. I sit a lot in the debugger (other people's programs) and I never see even SSE let alone all the other things that could happen. One day the output will change ;)
If you compile the code on said absolutely-latest-CPU, -mtune=native for GCC and Clang, -xHost for ICC.
I don't use MSVC, but /arch:AVX will get you the AVX instructions found on Sandy Bridge and Ivy Bridge. AFAIK, there is no generic "tune generated code for host" flag for MSVC, and AVX2 is not supported at all yet.
You'll probably need to pass optimization-level and vectorization flags to see more of an effect, but for the most part, the biggest gains will come when optimized libraries come out with new ASM- or intrinsic-based variants for the new ISA extension.
Intel generally updates it's Math Kernal Library (which includes a LAPACK implimentation) with each new architecture.
If you only want to compare intel to intel and want to look at linear algebra or FFT heavy workloads, that's a great place to start.
Also, I seem to remember reading that the x264 team got early access to Haswell and so were able to start optimizing their encoding routines for it. So if there's a benchmark based on that, that would be another good place to look.
Speaking as someone writing a bunch of numerical code, while the fma and avx2 stuff is neat, that's not the part I find exciting. Those alone just naively give 2-4x boost
The main exciting part of avx2 is that I can have more of a matrix in registers at a time. Depending on the details of the matrix multiply algs etc, this reduces the volume of loads and stores by some neat factor.
Likewise the support for gathers is neat, and makes for better performance with some of the standard matrix layouts that fundamentally have bad strides access.
What I'm really excited about is the parallel bit deposits / extract operations. They're meant for making it easy to write arbitrary bit permutation functions in a small number of rounds, but potentially could be used to support fast indexing into some nonstandard linear algebra layouts that have substantially better memory locality. I'm talking layouts that easily compete with blas / atlas etc with a lot less engineering work.
I'm really excited to get my hands on some haswell hardware in the coming months to experiment thusly.
Context for me being that I'm writing tools in Haskell to generate and run numerical codes and I think some of the things Haswell enabled are quite swell.
There's also that htm concurrency machinery that'd be neat to mess around with too.
BTW, I find Anandtech's coverage of CPUs to be the best since they actually dive into some of the architectural decisions. Interesting if you care about the "whys" behind the benchmarks.
One of the other things to note is support for hardware transactional memory. Applications won't be taking advantage of that for a while, but it could have a significant impact once libraries are rewritten to take advantage.
44 comments
[ 3.6 ms ] story [ 90.2 ms ] threadThe power savings might get me to upgrade my laptop though.
What is the market for desktop CPUs where the desktop buyers don't also have dedicated video cards which can do a almost a magnitude better job than the APU?
Small form factors, like the iMac or Mac mini. Apple is pretty influential in Intel's roadmap nowadays. See also how the next-gen mobile chipsets are getting more powerful onboard GPUs to drive Retina displays.
EDIT: it does go up to nearly 20 watts, depending, esp if you have the HDMI plugged in. Technically I think you can get more out of a NUC than a mini in terms of raw MIPs. They're PCs, not toys like RPI.
In practice, with the advent of compute shaders and opencl, there is very little intense serial work that can't be done in parallel. My workflow nowadays is (using python as an example)
Slow? (assuming we know why it is slow and it isn't just maligned algorithmic complexity making something a runtime exponential where you can use a quadratic) -> Put it in C++. Still slow? -> Parallelize into tasks and put in a work threadpool (assuming there is a lot of this kind of work happening, else just numcores / X threads do stuff). Still slow? -> Port over to opencl (or if memory copies are unnecessary, opengl compute shaders) and keep the old implementation for backwards compatibility with systems lacking them.
The way the market is going these days, consumer devices will soon almost all be based around low power/small footprint solutions(e.g. atom, mobile, arm). Heck, it probably won't be too long before we start seeing some serious SOC solutions(what could a raspberry pi type device do in 2 years with a 4 or 6 core arm at it's core). So, that kills margins on the consumer market more or less. Or, well, at least it becomes a race to the bottom. What's left is enterprise and "the cloud", where efficiency and iops still rule. For these companies, CPU speed isn't a bottleneck, it's mostly core and io density. They simply want to run more jobs in a smaller space, not necessarily run the jobs faster. So engineering teams are starting to look very closely at GPUs as a means to get a huge improvement in core density for certain situations at the cost of having to rethink some of the software stack. Putting the GPU on the same die as the CPU makes a lot of sense from this perspective.
It'll be interesting to watch. If nvidia does have an arm platform in the works, they may win this race, though intel does have a huge advantage with being able to run multiple foundries at one. Part of me wants to believe that intel is capable of doing much more with their APU solutions, but are simply waiting until the future of the market is clearer. Once that happens, they may be able to beat everyone else simply by timing the market on newer designs(like how intel beat AMD after screwing up with itanium and P4).
Note: Having a low power SOC type solution is another side effect of all this, but I don't think that's the primary motivator for Intel's efforts here. Maybe for the atoms, but not this chip.
If you can stand the sunk cost it's a LOT cheaper than AWS. Horses for courses YMMV etc.
I buy not-for-resale chips on a dodgy basis for fuzzing (MOAR VMS!) but on the whole, bucks per MIP, or MIPs per watt - who cares?
Mainly, whether MIPs per watt matters depends on where you can get your stuff racked ;)
(x as many as I could afford). That does look like a good chip, but dodgy engineering sample trays in 2013 you can prolly get twice as many cores. That means NO WARRANTY and like, not for work.
That should be a way to do something wrong and interesting.
Not to mention the 3930k has 6 cores whereas all of those have 4.
Unfortunately, it takes time to optimize code for each new architecture, and most benchmarks don't even bother with a recompile.
Not really griping that much; eventually people do do those kinds of benchmarks, but they do take time, and they're not really the target audience for someplace like Tom's. Understandable they would focus on gaming & general-use benchmarks.
I don't use MSVC, but /arch:AVX will get you the AVX instructions found on Sandy Bridge and Ivy Bridge. AFAIK, there is no generic "tune generated code for host" flag for MSVC, and AVX2 is not supported at all yet.
You'll probably need to pass optimization-level and vectorization flags to see more of an effect, but for the most part, the biggest gains will come when optimized libraries come out with new ASM- or intrinsic-based variants for the new ISA extension.
If you only want to compare intel to intel and want to look at linear algebra or FFT heavy workloads, that's a great place to start.
Also, I seem to remember reading that the x264 team got early access to Haswell and so were able to start optimizing their encoding routines for it. So if there's a benchmark based on that, that would be another good place to look.
The main exciting part of avx2 is that I can have more of a matrix in registers at a time. Depending on the details of the matrix multiply algs etc, this reduces the volume of loads and stores by some neat factor.
Likewise the support for gathers is neat, and makes for better performance with some of the standard matrix layouts that fundamentally have bad strides access.
What I'm really excited about is the parallel bit deposits / extract operations. They're meant for making it easy to write arbitrary bit permutation functions in a small number of rounds, but potentially could be used to support fast indexing into some nonstandard linear algebra layouts that have substantially better memory locality. I'm talking layouts that easily compete with blas / atlas etc with a lot less engineering work.
I'm really excited to get my hands on some haswell hardware in the coming months to experiment thusly.
Context for me being that I'm writing tools in Haskell to generate and run numerical codes and I think some of the things Haswell enabled are quite swell.
There's also that htm concurrency machinery that'd be neat to mess around with too.
Performance per watt is another story through ...
http://anandtech.com/show/7003/the-haswell-review-intel-core...