[–] kazagistar 12y ago ↗ Is there any plans to work hardware transactional memory into the mix? [–] kingkilr 12y ago ↗ Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no. [–] 4buser 12y ago ↗ Even new Intel Haswell's STM? [–] sanxiyn 12y ago ↗ Yes, Intel TSX too has a limited transaction size.
[–] kingkilr 12y ago ↗ Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no. [–] 4buser 12y ago ↗ Even new Intel Haswell's STM? [–] sanxiyn 12y ago ↗ Yes, Intel TSX too has a limited transaction size.
[–] 4buser 12y ago ↗ Even new Intel Haswell's STM? [–] sanxiyn 12y ago ↗ Yes, Intel TSX too has a limited transaction size.
[–] nn4 12y ago ↗ Obligatory anti STM hype links:http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.
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[ 2.8 ms ] story [ 28.4 ms ] threadhttp://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...
Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.