The linked article is a very lengthy argument for an incorrect conclusion.
The real answer is due to the low level design of CPU address mode generation circuitry. CPU's with "base plus offset" or "base plus index" addressing modes always (when using this address mode) add together two items to arrive at a final address in memory. So in order to access a value stored at the "base" address, one has to feed an "index" value through the hardware adder that results in the output address equaling the input address.
Well, 2+0 = 2, so the "index" value for the memory cell located at the "base" value is "base" + "index (zero)" => "base".
The concept just stuck in the higher level languages because it mapped neatly to the CPU hardware, and because the folks designing the higher level languages were already accustomed to thinking in the "base plus index" mindset.
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[ 1.5 ms ] story [ 14.1 ms ] threadThe real answer is due to the low level design of CPU address mode generation circuitry. CPU's with "base plus offset" or "base plus index" addressing modes always (when using this address mode) add together two items to arrive at a final address in memory. So in order to access a value stored at the "base" address, one has to feed an "index" value through the hardware adder that results in the output address equaling the input address.
Well, 2+0 = 2, so the "index" value for the memory cell located at the "base" value is "base" + "index (zero)" => "base".
The concept just stuck in the higher level languages because it mapped neatly to the CPU hardware, and because the folks designing the higher level languages were already accustomed to thinking in the "base plus index" mindset.