This looks really interesting from a quick skim. Also, it appears that their initial prototypes were built using Xilinx's Virtex FPGAs but the final model was built on Altera's Stratix V D5. I wonder what prompted the change - speed/power/amount of available logic? They seemed not to explain the switch in the paper (or if they did, it escaped my notice).
I asked some of the authors about this---it sounded like the primary reason was that, in the FPGAs they were considering, the Altera PCIe endpoint was much better behaved than the Xilinx one (due to excessive link training time, IIRC).
2 comments
[ 2.6 ms ] story [ 9.9 ms ] thread