Would Rosetta 2 have worked as well for x86 APX i.e. 32 GPRs instead of 16? (16x x86 regs fit in 32x Arm regs, whereas 32x in 32x is... much less of a fit)
x86 has... INT Ib INT1 INT3 INTO BOUND
Nowadays UD0 UD1 UD2 are in the SDM and APM. We also got UDB (D6), the one-byte variant that arrived with x86-64 for 64-bit mode. And we have always had UDW (FF FF), aka group #5 (1st FF) with a modrm byte of mod=11b…
Would Rosetta 2 have worked as well for x86 APX i.e. 32 GPRs instead of 16? (16x x86 regs fit in 32x Arm regs, whereas 32x in 32x is... much less of a fit)
x86 has... INT Ib INT1 INT3 INTO BOUND
Nowadays UD0 UD1 UD2 are in the SDM and APM. We also got UDB (D6), the one-byte variant that arrived with x86-64 for 64-bit mode. And we have always had UDW (FF FF), aka group #5 (1st FF) with a modrm byte of mod=11b…