No, this is panels from which interposers will be made. Which are now larger than chips and rectangular, so wasted edges from a 300mm wafer are high. The proposed size is much larger than chip-grade ingots. They don't…
MIPS had load const to high or low half. More that 40 years ago Transputer had shift-and-load 8 bit constants. Lots of ancient precedents for rare big constants.
Interesting idea. Effectively moving the extra decode stage in front of the Icache, making the Icache a bit like a CISC trace/microOp cache. On a 512b line you would add 32 bits to mark the instruction boundaries. At…
DRAM is not greatly affected by radiation, because the capacitors are large structures relative to radiation events. SRAM is affected, which is why SRAM arrays should always use SECDED ECC. The dominant cause of DRAM…
Hi David, thanks for the kind words. I still have the source for that I think, it was written around 1984 originally for a project of my own, then sold to Logitech, Zorland, and Borland (before I went to work for…
Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M chips. TSMC is in a position to command a…
Ironic. CMP was developed and perfected at IBM, who used it to make complex low volume products. Excellent insight. CMP and damascene metal (guess who!) really kicked CMOS into top gear.
No, this is panels from which interposers will be made. Which are now larger than chips and rectangular, so wasted edges from a 300mm wafer are high. The proposed size is much larger than chip-grade ingots. They don't…
MIPS had load const to high or low half. More that 40 years ago Transputer had shift-and-load 8 bit constants. Lots of ancient precedents for rare big constants.
Interesting idea. Effectively moving the extra decode stage in front of the Icache, making the Icache a bit like a CISC trace/microOp cache. On a 512b line you would add 32 bits to mark the instruction boundaries. At…
DRAM is not greatly affected by radiation, because the capacitors are large structures relative to radiation events. SRAM is affected, which is why SRAM arrays should always use SECDED ECC. The dominant cause of DRAM…
Hi David, thanks for the kind words. I still have the source for that I think, it was written around 1984 originally for a project of my own, then sold to Logitech, Zorland, and Borland (before I went to work for…
Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M chips. TSMC is in a position to command a…
Ironic. CMP was developed and perfected at IBM, who used it to make complex low volume products. Excellent insight. CMP and damascene metal (guess who!) really kicked CMOS into top gear.