There's Chisel (Scala based) the LowRisc team from Berkeley are using[1]. It can output Verilog and also compiles to cycle accurate simulators. There's also PSHDL from Karsten Becker[2] at TUHH. It's immature and seems…
There's Chisel (Scala based) the LowRisc team from Berkeley are using[1]. It can output Verilog and also compiles to cycle accurate simulators. There's also PSHDL from Karsten Becker[2] at TUHH. It's immature and seems…