There is a ton of technical info out there, but in a nutshell, the hardware is extremely optimized for I/O bandwidth, cache's are able to be accessed by more cores at a time (I think the L3 cache is 32-way accessible…
There is a ton of technical info out there, but in a nutshell, the hardware is extremely optimized for I/O bandwidth, cache's are able to be accessed by more cores at a time (I think the L3 cache is 32-way accessible…