> Also, in multicore CPUs, there are generally some spare cores that will get swapped in if a previously in-use core breaks. That sounds like a huge cost to bear. Looking at e.g. a Haswell die photo [1], there are just…
I agree, but asking this of Intel is the equivalent to asking Google to bare the details of their search ranking algorithm so that we could understand some odd search result. The clever tricks and optimizations they do…
In fact, hasn't been true since the Pentium Pro. Agner Fog's excellent microarchitecture docs [1] indicate that the PPro (which was a 3-wide machine, and the first out-of-order x86) could find 3 instructions per cycle…
> Also, in multicore CPUs, there are generally some spare cores that will get swapped in if a previously in-use core breaks. That sounds like a huge cost to bear. Looking at e.g. a Haswell die photo [1], there are just…
I agree, but asking this of Intel is the equivalent to asking Google to bare the details of their search ranking algorithm so that we could understand some odd search result. The clever tricks and optimizations they do…
In fact, hasn't been true since the Pentium Pro. Agner Fog's excellent microarchitecture docs [1] indicate that the PPro (which was a 3-wide machine, and the first out-of-order x86) could find 3 instructions per cycle…